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project.setAnalysisConditions(conditions = 'worstcase') |
setCaseAnalysis(value =
...
'value', netList =
...
netList)
This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
|---|---|---|
value | unsignedstring | The valid constant. Values can be 0 ‘0' or 1'1’ |
netList | string | Specifies how to get one or several nets. A valid argument can be: |
Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered. The constant value is propagated through the network as long as a controlling value for the traversed logic is at the constant value.
Example:
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In the example above, two clocks (clk[0] and clk[1]) are connected to the inputs of the multiplexer, but only clk[1] is propagated through the output after setting the constant value on the selection signal (sel).
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project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(value = '1', netList = 'getNet(sel)') |
clearTimingConstraints()
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Name | Type | Description |
target | string | Mandatory. The argument that specifies how to get a clock related point. A valid argument can be: |
name | string | Optional. User clock name of the created clock, default name is target_str |
period | float | Mandatory. Period for the clock waveform. Must be positive, default value is period/2 |
rising | float | Mandatory if falling is defined. Otherwise, it is optional. Rising edge for the clock waveform. The range is defined as [0, period[ The default value is 0. |
falling | float | Optional. Falling edge for the clock waveform. The range is defined as ]rising, rising + period]. The default value is period/2. |
Examples:
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In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :
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Frequency-based and edge-based relationships are mutually exclusive. |
Examples:
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In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. However note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:
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project = createProject()
project.load('routed.nym')
project.createClock(source = 'getPort(Clk)', name = 'Clk', period = 10)
project.createGeneratedClock(source = 'getRegisterClock(clk_reg)', target = 'getRegisterClock(reg2)', name = 'clk1', divideBy = 2)
or
project.createGeneratedClock(source = 'getClock(Clk)', target = getRegisterClock(reg2)', name = 'clk1', edges = [2, 4, 6]) |
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The diagram of the above command would be:
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Clock Relationship
setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)
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