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It is recommended to rather use python method addMemoryInitialization described in /wiki/spaces/~814749387/pages/48660481 as it is compliant with inferred and instantiated memories.

Please have a look at Impulse 23.1 Training Package : Application Note Init/Ram project.

Memory Inference

In order to infer a memory instead of instantiating a NanoXplore primitive (advantage is the user can choose with the same RTL code to map this memory in RF, RAM, RAM_ECC, … thanks to NXpython constraints), it is recommended to follow TrainingPackage Design/MemInfer examples providing inference for ROM, SRAM, DPRAM with and without ECC.

Please have a look at Impulse 23.1 Training Package : Application Note Design/MemInfer project.

Hierarchy

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The logic depth of a design must be controlled. the method reportDesignComplexity is very helpful to have an overview.It

Please have a look at Impulse 23.1 NxPython Specification reportDesignComplexity method.

How to use NXpython constrains methods

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Complexity Complexity

Complexity

In order to map an operator into LUT, CY or DSP, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the operator model or instance in operators.rpt report. For instance, “ | Operator 'add_3u_3u' | : add_L25 (line 25 in …”, model name is “add_3u_3u” and instance name is “add_L25”.

• Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(add_3u_3u)','ADD','DSP')” or p.addMappingDirective('getInstances(add_L25)','ADD','DSP')”, and relaunch the project.

• Check in operators.rpt report the constraint matched with the desired instance.

Please have a look at Training Package Application Note MappingDirective/Operator project.

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get complexity for each module of the design, check the detailed hierarchy of the design.

Complexity is given for each module with the sum of the complexity of each sub-module and the module itself.

For instance:

08:50:49:info     |     --------------------------------------------
08:50:49:info     |     - Detailed Hierarchy Statistics            -
08:50:49:info     |     --------------------------------------------
08:50:49:info     |     ~                   hierarchical
08:50:49:info     |                         Resources:
08:50:49:info     |                           NX_LUT : 13
08:50:49:info     |                           NX_DFF : 73
08:50:49:info     |                           NX_IOB : 51
08:50:49:info     |                           NX_BFR : 99
08:50:49:info     |                           NX_WFG : 3
08:50:49:info     |     ~                   |-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]
08:50:49:info     |                         |-> Resources:
08:50:49:info     |                         |->   NX_LUT : 3
08:50:49:info     |                         |->   NX_DFF : 23
08:50:49:info     |     GEN_HIER0_ROW-0     |   |-> timing_pipe(X2A98C8C6) [ GEN_HIER0|GEN_ROW[0].ROW_PIPE ]
08:50:49:info     |                         |   |-> Resources:
08:50:49:info     |                         |   |->   NX_DFF : 5
08:50:49:info     |     ~                   |   |-> timing_pipe(X2A98C8C6) [ GEN_HIER0|GEN_ROW[1].ROW_PIPE ]
08:50:49:info     |                         |   |-> Resources:
08:50:49:info     |                         |   |->   NX_DFF : 5

How to use NXpython constrains methods

Mapping directive

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Mapping_directive_Operator Mapping_directive_Operator

Operator

In order to map an operator into FELUT, RF, RAM or RAM_ECCCY or DSP, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the memory operator model or instance in memoriesoperators.rpt report. For instance, “ | Ram Operator 'RAMadd_s3u_mem3u' Analysis:| : add_L25 (line 25 in …”, model name is “RAM_s_mem” “add_3u_3u” and instance name is “add_L25”.

• Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(RAM_s_memadd_3u_3u)','ADD','DSP')” or p.addMappingDirective('getInstances(add_L25)','RAMADD','RAM_ECC')”, and relaunch the project.

• Check in memories.rpt report the constraint matched with the desired instance.

Please have a look at Training Package Application Note MappingDirective/Memory project.

Instance placing

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In order to place manually an inferred DSP in a CGB spot, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the DSP name DSP')”, and relaunch the project.

• Check in operators.rpt report . For instance, “in line : mult_L28 (line 28 in […]”, name is “mult_L28”.

• Add the constraint specifying DSP spot (CGB coordinates and L or R respectively for Left and Right), for instance “p.addDSPLocation('DSP_mult_L28','CGB[8x8]:R')”, and relaunch the project.

• Check in preplaced.rpt report the constraint matched with the desired instance.

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• the constraint matched with the desired instance.

Please have a look at Impulse 23.1 Training Package : Application Note MappingDirective/Operator project.

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Mapping_directive_Memory Mapping_directive_Memory

Memory

In order to map an operator into FE, RF, RAM or RAM_ECC, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the memory model in memories.rpt report. For instance, “ | Ram 'RAM_s_mem' Analysis:”, model name is “RAM_s_mem”.

• Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(RAM_s_mem)','RAM','RAM_ECC')”, and relaunch the project.

• Check in memories.rpt report the constraint matched with the desired instance.

Please have a look at Impulse 23.1 Training Package : Application Note PlacingConstraint MappingDirective/DspLocation Memory project.

Instance placing

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Dsp_placing Instance_placing_

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Dsp_placing

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DSP placing

In order to place manually an inferred RAM DSP in a CGB spot, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the RAM DSP name in memoriesoperators.rpt report. For instance,“ | RAM Generation for g_loop[0].i_RAM_example|s_mem”, name is “g_loop[0].i_RAM_example|s_mem|ram0_0_0_0”“in line : mult_L28 (line 28 in […]”, name is “mult_L28”.

• Add the constraint specifying RAM DSP spot (CGB coordinates and L or R respectively for Left and Right), for instance “p.addRAMLocationaddDSPLocation('g_loop[0].i_RAM_example|s_mem|ram0_0_0_0DSP_mult_L28','CGB[8x8]:R')”, and relaunch the project.

• Check in preplaced.rpt report the constraint matched with the desired instance.

Please have a look at Impulse 23.1 Training Package : Application Note PlacingConstraint/RamLocation DspLocation project.

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RAM placing

In order to place manually an automatically created WFG inferred RAM in a CKG CGB spot, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the RAM name in lowskewmemories.rpt report. For instance, “rg~clk_divp2 from instance wfg_B_clk_divp2”, name is “wfg_B_clk_divp2,“ | RAM Generation for g_loop[0].i_RAM_example|s_mem”, name is “g_loop[0].i_RAM_example|s_mem|ram0_0_0_0”.

• Add the constraint specifying RAM spot (CGB coordinates), for instance “p.addRingLocationaddRAMLocation(' wfg_B_clk_divp2','CKG3.WFG_C1g_loop[0].i_RAM_example|s_mem|ram0_0_0_0','CGB[8x8]')”, and relaunch the project.

• Check in preplaced.rpt report the constraint matched with the desired instance.

Please have a look at Impulse 23.1 Training Package : Application Note PlacingConstraint/RingLocation project.

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In order to place manually an inferred TILE instance like DFF, LUT or CY, follow the following steps:

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Launch your design for the first time without constraint.

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Grab the register name in RegisterSummary.rpt report or in timing files. For instance, i_cpt_0|s_cpt_out_reg[5]”.

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Add the constraint specifying TILE spot (TILE coordinates), for instance “p.setSite('i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]'”, and relaunch the project.

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RamLocation project.

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Instance_placing_Ring_placing Instance_placing_Ring_placing

Ring placing

In order to place manually an automatically created WFG in a CKG spot, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the RAM name in lowskew.rpt report. For instance, “rg~clk_divp2 from instance wfg_B_clk_divp2”, name is “wfg_B_clk_divp2”.

• Add the constraint specifying RAM spot (CGB coordinates), for instance “p.addRingLocation(' wfg_B_clk_divp2','CKG3.WFG_C1')”, and relaunch the project.

• Check in preplaced.rpt report the constraint matched with the desired instance.

Please have a look at Impulse 23.1 Training Package : Application Note PlacingConstraint/Site RingLocation project.

Floor planning

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placing

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placing

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Tile placing

In order to get complexity for each module of the designplace manually an inferred TILE instance like DFF, LUT or CY, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the module and instance register name in hierarchyRegisterSummary.rpt report or in timing files. For instance, “| |-> timing_pipe(X2A98C8C6) [ GEN_HIER0|GEN_ROW[0].ROW_PIPE ]”, module name is timing_pipe(X2A98C8C6)” and instance name is “ [ GEN_HIER0|GEN_ROW[0].ROW_PIPE i_cpt_0|s_cpt_out_reg[5]”.

• Add the constraint specifying TILE spot (TILE coordinates), for instance “p.addModulesetSite('timing_pipe(X2A98C8C6)', 'GEN_HIER0.GEN_ROW[0].ROW_PIPE', 'GEN_HIER0_ROW-%')i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]'”, and relaunch the project.

• Check in hierarchypreplaced.rpt report the constraint matched with the desired instance.

Please have a look at Impulse 23.1 Training Package : Application Note PlacingConstraint/Region Site project.

Floor planning

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Floor_planning_Constrain_module Floor_planning_Constrain_module

Constrain Module

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• Launch your design for the first time without constraint.

• Grab the module name in hierarchy.rpt report. For instance, “| ~ |-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”, name is “|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”.

• Add the constraint specifying area coordinates, for instance “p.constrainModule('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','GEN_HIER0_ROW_M','Soft',9,6,2,3,'GEN_HIER0_ROW_R',False)”, and relaunch the project.

• Check in hierarchy.rpt report the constraint matched with the desired instance.

Please have a look at at Impulse 23.1 Training Package : Application Note PlacingConstraint/Region project.

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• Launch your design for the first time without constraint.

• Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.

• Add the constraint specifying area coordinates, for instance “p.constrainPath('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','PIPE_REG_M','Soft',9,6,2,3,'PIPE_REG_R',False)”, and relaunch the project.

• Check in hierarchy.rpt report the constraint matched with the desired instance.

Please have a look at Impulse 23.1 Training Package : Application Note PlacingConstraint/ConstrainPath project.

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• Define the macro IP as the top cell.

• Define a minimum aperture and all needed constraints as it was a global project to reach specifications. Save the project file after routed steps.

• Run the project until Placing 3/5 step and use saveIP method to save the preplaced IP.

• Do not declare the macro IP entity file in the global project. Instead, add the macro IP as a blackbox, specifying coordinates of the top left corner of the macro IP aperture in the global project, for instance “p.addBlackBox('switch_counter',IP','../switch_counter_preplaced.nymjson','g_inst.i_switch_counter_0:1x8')”.

• Check in synthesize. log llog the constraint matched.

Please have a look at Impulse 23.1 Training Package : Application Note PlacingConstraint/Preplace project.

STA constraints

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Sta_constraints_Clock_declaration Sta_constraints_Clock_declaration

Clock declaration

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Please have a look at Impulse 23.1 Training Package : Application Note StaConstraint/GeneratedClock project.

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• Grab the clock name getting the hierarchy path to the generated clock.

  • Add the constraint specifying clock parameters, for instance “p.createGeneratedClock(getClock('clk_main'),getRegisterClock('i_clock_0|counter_reg[0]'), 'clk_fabric',{'DivideBy': 2})”.

• Check timing files are created for this new clock domain.

Please have a look at Impulse 23.1 Training Package : Application Note StaConstraint/GeneratedClock project.

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• Launch your design for the first time without constraint.

• Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.

• Add the constraint specifying area coordinates, for instance “p.addFalsePath('getRegisters(module0|submodule0|pipe_reg[0])','getRegisters(module0|submodule0|pipe_reg[0])')”, and relaunch the project.

• Check in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timingt report the path no longer appears.

Please have a look at Impulse 23.1 Training Package : Application Note StaConstraint/FalsePath project.

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