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Please have a look at Training Package : Application Note Design/LowskewManagement project.
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PLL outputs are connected to WFG of the same CKG. User can either instantiate a WFG or let the tool instantiate a WFG in bypass mode by itself. WFG outputs are connected to the low-skew network. |
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Do not use NX_BD(global_lowskew) or NX_GCK(CSC) with an input low-skew signal. |
In case of clock gating or clock mux, it is recommended to implement the following architecture:
Clock Gating:
MEDIUM/LARGE: Use a NX_CKS to gate a clock system signals with a command common signal.
ULTRA: Use a NX_GCK_U in Clock Switch CKS mode to gate a clock system signals with a command common signal.
Clock MUX:
ULTRA: Use a NX_GCK_U in Clock MUX MUX mode to switch between 2 clock system signals with a command common signal.
Please have a look at Training Package : Application Note Component/ClockSwitch project.
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It is highly recommended to not cascade GCK as it is not natively supported by the architecture. User can cascade GCK anyway by allowing the associated option leading to a longer clock insertion path. |
Reset management
Like clocks, reset are generally spread to the whole design through the low-skew network because of high fanout too.
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