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Use a pad directly connected to the closest CKG (these pads are suffixed by _CLK). Either the user instantiates a PLL or a WFG in the design or the tool instantiates automatically a WFG in bypass mode.
MEDIUM/LARGE: Use a common pad or internal logic and use a buffer NX_BD in global_lowskew mode.
ULTRA: Use a common pad or internal logic and use a NX_GCK_U in Common to System Converter CSC mode.
Please have a look at Training Package : Application Note Design/LowskewManagement project.
In case of clock gating or clock mux, it is recommended to implement the following architecture:
Clock Gating:
MEDIUM/LARGE: Use a NX_CKS to gate a clock system signals with a command common signal.
ULTRA: Use a NX_GCK_U in Clock Switch CKS mode to gate a clock system signals with a command common signal.
Clock MUX:
ULTRA: Use a NX_GCK_U in Clock MUX MUX mode to switch between 2 clock system signals with a command common signal.
Reset management
Like clocks, reset are generally spread to the whole design through the low-skew network because of high fanout too.
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The logic depth of a design must be controlled. the method reportDesignComplexity is very helpful to have an overview.
It
Please have a look at NxBeta_NXpython specification Impulse 23.1 NxPython Specification reportDesignComplexity method.
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