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Attribute:
NxInit
NxPort
NxUse
SynKeep
SynPreserve
Board:
Scope
SwichBlink
ThermalSensor
Component
ClockSwitch
Ddfr
DspConfig
IoConfig
PllConfig
RamConfig
RfbConfig
Service
Soc
WfgConfig
Design
DelayIo
DspCascaded
DspMultAcc
DspTranspose
LowskewManagement
MemInfer
Init
Ram
Ip
CrossDomain
Ddr2Dfi
HsslEsistream
R5AxiMaster
R5AxiSlave
R5Jtag
Serdes
SpacewireLoopback
SpacewireRoadmap
SpacewireRx
MappingDirective
Adder
BlackBox
Memory
Pad
Parameter
Registered
PlacingConstraint
Aperture
ConstrainPath
DspLocation
ExportSites
Focus
Obstruction
PreplaceIp
RamLocation
Region
RingLocation
Site
ProcessingSystem
Interruptions
Watchdog
StaConstraint
CaseAnalysis
ClockGroup
DelayPath
FalsePath
GeneratedClock
InputOutputDelay
ReportPath
...
Board check: No board purpose for this testcase.
Ddfr
Description:
The user can use double data rate input/output using NanoXplore macro cells in the design code.
For input double data rate, macro cell NX_IDDFR generates 2 single data rate from 1 double data rate.
For output double data rate, macro cell NX_ODDFR generates 1 double data rate from 1 single data rate.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-ULTRA |
Embedded | No |
Simulation | Yes |
Attributes |
|
IP | NX_IDDFR NX_ODDFR |
Methods |
|
Table: Component Ddfr environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI the DDFR cells close to the pad.
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Simulation check: NanoXplore macro cells manage double data rate
Board check: No board purpose for this testcase.
DspConfig
Description:
The user can make operations using NanoXplore DSP macro cells in the design code.
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