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Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation |
addBank |
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addBanks |
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addBlackBox |
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addDSPLocation |
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| X |
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addFalsePath |
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addFile | X |
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addFiles | X |
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addHSSLLocation | ||||||
addIP | X |
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addMappingDirective |
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addMaxDelayPath |
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addMemoryInitialization |
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| X |
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addMinDelayPath |
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addModule |
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addMulticyclePath |
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addPLLLocation |
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addPad |
| X | X |
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addPads |
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addParameter | X |
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addParameters | X |
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addPin |
| X | X |
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addPins |
| X | X |
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addRAMLocation |
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| X |
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addRingLocation |
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| X |
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addRingLocations |
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| X |
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addVerilogIncludeDirectories | X |
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addVerilogIncludeDirectory | X |
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addVlogDefine | X |
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addVlogDefines | X |
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addWFGLocation |
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adjustAperture |
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applySdcFile |
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clearBanks |
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clearFabricPrePlaceConstraints | X | |||||
clearPLLs |
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clearPads |
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clearPins |
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clearWFGs |
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confineModule |
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| X |
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constrainModule |
| X | X |
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constrainPath |
| X | X |
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createAnalyzer |
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createClock |
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createGeneratedClock |
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createObstruction |
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createRegion |
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createSimulator |
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destroy | X |
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destroyObstruction | X |
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destroyRegion | X |
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developCKGs |
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exportAsIPCore | X |
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exportRegions | X |
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exportSites | X |
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generateBitstream |
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| X |
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generateSTANetlist | X |
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getAnalyzer | X | |||||
getDirectory | X |
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getErrorCount | X | |||||
getHierInfo | X | |||||
getLowskewSignals | X |
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getProject | X | |||||
getRemarkCount | X | |||||
getTimingUnit | X |
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getTopCellName | X |
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getVariantName | X |
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getWarningCount | X | |||||
initRegister |
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limitLowskew |
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listAvailableLocations | X |
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load | X |
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modifyPad | X | |||||
modifyRegion |
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place | X |
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progress | X |
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printError | X | |||||
printHierInfo | X | |||||
printRemark | X | |||||
PrintText | X | |||||
PrintWarning | X | |||||
rejectLowskew | X |
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removeFile | X |
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removeFiles | X |
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removeSoftModules | X | |||||
reportDesignComplexity | X | |||||
reportInstances | X |
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reportLowskewSignals | X |
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reportPorts | X |
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reportRegions | X |
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reportRegisters | X |
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resetTimingConstraints | X |
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route | X |
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save | X |
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setAnalysisConditions |
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setAperture |
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setCaseAnalysis |
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setClockGroup |
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setDescription | X |
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setDeviceID |
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| X |
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setDirectory | X |
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setFalsePath |
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setFocus |
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setGCKCount |
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setInputDelay |
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setMaxDelay |
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setMinDelay |
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setMulticyclePath |
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setOption | X |
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setOptions | X |
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setOutputDelay |
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setSite |
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setTopCellName | X |
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setVariantName | X |
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synthesize | X |
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translateAperture |
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| Code Block | ||
|---|---|---|
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project = createProject('/home/user/example/vhdl/simple')
project.load('synthesized.nym') |
modifyPad(name, parameters)
This method is used to modify the configuration of an existed pad.
This method takes the same parameters as addPad method.
Parameters that only affect the configuration and not the placing can be changed at any time.
Arguments:
Name | Type | Description |
name | string | IO name. |
parameters | dictionary | Configuration parameters. |
| Note |
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After synthesis, the following parameters cannot be modified : location, differential and registered. |
Example:
| Code Block | ||
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project.addPad('output[0]',{'location':'IOB10D09P', 'standard': 'LVCMOS', 'drive' :'2mA', 'slewRate':'Slow'}) project.modifyPad('output[0]',{'drive' :'16mA', 'slewRate':'Fast'}) |
modifyRegion(name, column1, row1, width, height, exclusive)
This method is used to modify the location or the size of an existed region.
Arguments:
Name | Type | Description |
name | string | name of the region. |
column1 | integer | the number of the most left column of the region. |
row1 | integer | the number of the most top row of the region. |
width | integer | the width of the region (in number of columns). |
height | integer | the height of the region (in number of rows). |
exclusive | boolean | region is exclusive or not |
Example:
| Code Block |
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project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12, 19, 3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3) |
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