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Attribute: Attributes can be inserted in the design in order to add a constraint on a register, a memory, …
Board: Designs to program NanoXplore evaluation boards (DevKit / BringUp).
Component: Multiple configurations for NanoXplore primitives.
Design: Various types of designs without any specific IP.
Init: Memory initialization
Ip: Designs implementing NanoXplore Ips.
MappingDirective:Directive of elements mapping in NanoXplore primitives.
Pad: Pad configurations.
PlacingConstraint: Constraints for manual placing of NanoXplore primitives.
ProcessingSystem: Communication between Programmable Logic and Processing System.
StaConstraint: Constraintsfor static time analysis.
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Attribute:
NxInit
NxPort
NxUse
SynKeep
SynPreserve
Board:
Scope
SwichBlink
ThermalSensor
Component
ClockSwitch
DspConfig
IoConfig
PllConfig
RamConfig
RfbConfig
Service
Soc
WfgConfig
Design
DelayIo
DspCascaded
DspMultAcc
DspTranspose
LowskewManagement
MemInfer
Init
Ram
Ip
CrossDomain
Ddr2Dfi
HsslEsistream
R5AxiMaster
R5AxiSlave
R5Jtag
Serdes
SpacewireLoopback
SpacewireRoadmap
SpacewireRx
MappingDirective
Adder
BlackBox
Memory
Pad
Parameter
Registered
PlacingConstraint
Aperture
ConstrainPath
DspLocation
ExportSites
Focus
Obstruction
PreplaceIp
RamLocation
Region
RingLocation
Site
ProcessingSystem
Interruptions
Watchdog
StaConstraint
CaseAnalysis
ClockGroup
DelayPath
FalsePath
GeneratedClock
InputOutputDelay
ReportPath
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Variant | NG-ULTRA |
Embedded | No |
Simulation | NoYes |
Attributes |
|
IP | NX_SERVICE_WRAP |
Methods | createClock |
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The user can configure pads with many parameters using addPad or modifyPad NXpython method.
The following parameters can be set by the method:
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Hereafter an example of using the method addPad to constrain create a pad:
| Code Block |
|---|
p.addPad('input[0]’,{'location':'IOB10_D09P', 'standard': 'LVCMOS'} ) |
User is also able to modify the pad parameters once the pad is created.
Hereafter an example of using the method modifypad to modify a pad:
| Code Block |
|---|
p.modifyPad('input[0]',{'standard': 'SSTL', 'drive' :'I'}) |
Environment:
Here after the table of compliances for this testcase.
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Table: Pad Parameter environment
Option: There is one option to check the impact of this constraint: No option is available for this testcase
No option: Final parameters are the one defined before first progress steps.
Modifypad: Final parameters are the one modified before routing.
NanoXmap check: After project launching, the user can check in progress.rpt that IOs get the defined parameters. Initial ones or modfied if option is set.
| Code Block |
|---|
| +-----------+------+------------+----------+---------+-----------+------------------------+----------+---------------+--------------+-------+
| | Name | I/O | Location | Standard | Voltage | Drive | Termination | SlewRate | DelayLine | Differential | Turbo |
| | | | | | | | R / Weak / Reference | | In / Out | | |
| +-----------+------+------------+----------+---------+-----------+------------------------+----------+---------------+--------------+-------+
| | input[2] | In | IOB10_D03N | SSTL | 2.5V | CatI | None / PullUp / - | Fast | False / False | False | False |
| | input[3] | In | IOB11_D04P | HSTL | 1.8V | CatII | None / PullUp / - | Medium | False / False | False | False |
| | input[5] | In | IOB10_D04N | LVCMOS | 2.5V | 16mA | None / PullUp / - | Medium | False / False | False | False |
| | input[4] | In | IOB10_D09N | LVCMOS | 2.5V | 8mA | None / PullUp / - | Medium | False / False | False | False |
| | output[4] | Out | IOB5_D05P | LVCMOS | 1.5V | 8mA | None / PullUp / - | Medium | False / False | False | False |
| | output[5] | Out | IOB4_D07P | LVCMOS | 2.5V | 16mA | None / PullUp / - | Medium | False / False | False | False |
| | output[2] | Out | IOB4_D03P | SSTL | 2.5V | CatI | None / PullUp / - | Fast | False / False | False | False |
| | output[3] | Out | IOB5_D05N | HSTL | 1.5V | CatII | None / PullUp / - | Medium | False / False | False | False |
| | input[0] | In | IOB10_D09P | LVCMOS | 2.5V | 2mA | 35 / PullUp / Floating | Slow | False / True | False | True |
| | input[1] | In | IOB10_D10P | LVDS | 2.5V | Undefined | 100 / PullUp / VT | Medium | True / False | True | False |
| | output[0] | Out | IOB4_D01P | LVCMOS | 2.5V | 2mA | 35 / PullUp / Floating | Slow | False / True | False | True |
| | output[1] | Out | IOB4_D06P | LVDS | 2.5V | Undefined | 100 / PullUp / VT | Medium | True / False | True | False |
| +-----------+------+------------+----------+---------+-----------+------------------------+----------+---------------+--------------+-------+
|
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NanoXmap check: After project launching, the user can check in the GUI that NX_DFR are instantiated if the option Registered is set. Otherwise, NX_DFF are instantiated.
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In the port report, user can observe the applied registered requirements:
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Simulation check: No simulation environment is available for this testcase.
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Board check: No board purpose for this testcase.
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ProcessingSystem
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Interruptions
Description:
The user can specify unrelated clocks using setClockGroup NXpython method or calling SDC constraint.The impact is during STA, no timing file is place manually a register into a tile using setSite NXpython method.
Only a tile can be set, not a precise spot into this tile.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP |
|
Methods |
Table: ProcessingSystem Interruptions environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI all connections with the SOC interface.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
Watchdog
Description:
The user can place manually a register into a tile using setSite NXpython method.
Only a tile can be set, not a precise spot into this tile.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP |
|
Methods |
Table: ProcessingSystem Interruptions environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI all connections with the SOC interface.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
StaConstraint
CaseAnalysis
Description:
The user can specify a case analysis for the STA using setCaseAnalysis NXpython method.
The impact is during STA, constrained net will be interpreted as a constant equal to the specified value.
Hereafter an example for this NXpython method:
| Code Block |
|---|
p.setCaseAnalysis(value = '0', netList= getNet('cmd')) |
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | setCaseAnalysis createClock setClockGroup getClockNet getNet |
Table: StaConstraint ClockGroup environment
Option: There are two options to check the impact of this constraint:
No option: STA is launched only with createdClock.
CaseAnalysis0: cmd net is considered as a 0 for STA.
CaseAnalysis1: cmd net is considered as a 1 for STA.
NanoXmap check: After project launching, the user can check wich domain appear in STA reports.
No option: Both clk1 and clk2 domains are reported
CaseAnalysis0: only clk2 domain is reported
CaseAnalysis1: only clk1 domain is reported
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
ClockGroup
Description:
The user can specify unrelated clocks using setClockGroup NXpython method or calling SDC constraint.
The impact is during STA, no timing file is generated between the 2 clock domains.
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Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock setClockGroup getClock |
Table: StaConstraint ClockGroup environment
Option: There is one are two option to check the impact of this constraint:
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