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clearTimingConstraints()

This method is used to reset clear all design constraints from the current project.
Reseted Cleared constraints can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

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p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.resetTimingConstraintsclearTimingConstraints()

Clock Creation

createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )

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