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Application Note
NG-ULTRA
bitstream loading security
Ver 1.0.0
Jan 2022
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| Table of Contents |
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Revision | Date | Editor | Modification |
1.0.0 | 04/02/2022 | PN | Initial Document |
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Reference | Description | Version |
RD1 | NG-ULTRA_BringUp_UserGuideV1.3 | V1.3 |
RD2 | NG_ULTRA_BitstreamLoadingSecurity_v1.0.0 package | V1.0.0 |
RD3 | NxBase2_v2.5.1-UL1 | V2.5.1 |
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Acronyms | Description |
ASW | Application Software |
BL0 | Boot Loader stage 0 |
BL1 | Boot Loader stage 1 |
BSM | Bitstream Manager |
CMIC | Configuration Memory Integrity Check |
CTR | Counter mode for block encryption |
DMA | Direct Memory Access |
DSP | Digital Signal Processor |
eROM | embedded ROM |
OTP | One Time Programmable (memory) |
ROM | Read Only Memory |
SoC | System on Chip |
SPI | Serial Peripheral Interface |
SPW | SpaceWire |
TCM | Tightly Coupled Memory |
TMR | Triplar Modular Redundancy |
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This application note, the reference designs and the associated scripts are intended to show NG-ULTRA FPGA bitstream loading security
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The NG-ULTRA component is composed of a large embedded FPGA and a digital processor subsystem based on ARM Cortex R52 cores. The bitstream manager (BSM) manages the FPGA fabric configuration.
Fig 1 – NG-ULTRA bloc diagram
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NG-ULTRA FPGA bitstream security is managed through the implementation of encryption mechanisms applied to the data to be protected. Security function that encodes a digital data using a secret encryption key, making the encoded data unintelligible unless it is decoded using a decryption key.
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Hardware:
NG-ULTRA Bring-up board
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Nxmap
Nxbase2
Security loader test package tools reference designs, scripts and binary files
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Please install the plugins full options to enable the loading of BTS file with NxBase2.
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nxbase2_cli/plugins
nxbase2_cli/nxbase2/plugins
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Bypass mode
Mode useful to test and debug, to bypass all security process.
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Name | Jumper | Value | Comment |
MODE1 MODE0 | J43 J42 | 0 0 | Mode Normal 0 FPGA: JTAG SOC: SPW, SPI Flash, UART |
MODE1 MODE0 | J43 J42 | 0 1 | Mode Normal 1 FPGA: SL_PAR_16, JTAG SOC: SPW, SPI Flash, UART |
MODE1 MODE0 | J43 J42 | 1 0 | Mode FPGA only FPGA: SL_PAR_16, JTAG |
MODE1 MODE0 | J43 J42 | 1 1 | Mode Test |
Tab 3 – Configuration mode selection
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Note: At power ON, all voltage LEDs have to be lighted.
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Bring-up board user GPIOs
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Note: User GPIOs are activated low
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To configure the fabric, the BSM uses rows of drivers. Each driver row manages a subset of logical rows. Each driver row is managed by a Loader module. This Loader module includes all FSM to access to configuration memory.
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A bitstream is a collection of Frames. Each frame as a header and a body. Frame header is a 32b word protected by EDAC. A bitstream includes 2 CRC, Frame CRC that checks the integrity of each fabric configuration frame and Bitstream CRC that checks the integrity of the whole bitstream.
Fig 2 – BSM bloc diagram
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Test_001 is an example of loading a non-encrypted bitstream with security mode enabled and disabled.
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The loader OTP stores security related data such as keys, seeds for key generation, identifier, anti-rollback counter, secure mode configuration.
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Test_004 dump the OTP memory.
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The lifecycle value is stored in the OTP memory. It determines the bitstream configuration interface and the type of BSM accesses authorized and the type of bitstream (crypted or encrypted).
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Note: The direct access is proceeded by direct engine with BTS file and the frame access is proceeded by frame engine with BBS or NXB file.
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A cyphered bitstream contains the rollback counter. Deciphering engine compares it to the anti-rollback counter stored into the OTP memory. The check algorithm depends of the life-cycle.
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Test_005 program the security data, lifecycle data, encryption keys and anti-rollback counter.
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Depending on the lifecycle, the encryption must be used to properly load a bitstream.
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