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NxScope generator Generator GUI
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After generating your customised NxScope IP Core, you must instantiate it in your designDesign.
The I/O Input and Ouput signals to be connected are as follows:
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Name | Type | Description |
CLK | std_logic | User Clock |
ENA | std_logic | Enables the clock for all NxScope internal logic, including trigger and capture. Can be tied to ‘1’ if not used |
TRIG_LINES | std_logic_vector | User defined (1 to 32-bit) |
DATA_LINES | std_logic_vector | User defined (2 to 240-bit) |
TRIG_IMMEDIATE | std_logic | Can be optionally used to resume a pending capture when the trigger condition can’t be met. Starts an immediate capture when going high |
Outputs
The
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NxScope IP Core outputs can optionally be used
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as
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Status Information.
Name | Type | Description |
TRIG_ARMED | std_logic | Can be optionally used to monitor the NxScope internal status |
DONE | std_logic | High when the capture is complete. Can be used as status-bit |
FIRST_LEVEL_TRIG_OK | std_logic | High after the first-level trigger condition has been met. Can be used as status-bit to inform about the current state of the analyser when a two-level trigger is selected and, for example, connected to a LED |
CURRENT_CAPTURE_SET | std_logic_vector(3 downto 0) | Available exclusively in “Multiple windows” mode. These 4 bits form a counter that is incremented whenever a new window capture is started. Beyond 15 windows, the counter wraps around. Can be used as status bits to monitor the progress of the capture windows. |
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Create a Custom NxScope IP Core
The NxScope generator is a GUI where you can Generator interface enables you to define all available parameters of the logic analyzeranalyser.
In order to launch the NxScope generatorGenerator, launch first the NXcore GUI (by typing the “nxcore” command at the prompt, and then, select the “NxScope” icon on the GUI left top side.
The next figure is a screen capture of the NXcore / NxScope generator Generator GUI. All customizable parameters are available in this single page. Anchor
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When all NxScope parameters are set, the IP Core can be generated by pressing the « generate » command, in the bottom-right part of the window.
Entity Name
The NxScope generator Generator generates a VHDL encrypted file. The entity name is entered here. The VHDL path and file name are chosen with the “Generate” (bottom-right of the window).
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This setting allows to define the length of the capture windows when “Capture mode” = “Multiple windows”.
Pre-trigger_
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samples: integer range 0 to capture_depth-1
When “Capture mode” is set to “Pre-trigger” and “Multiple level trigger” is “false” it’s possible to sample data before reaching the trigger condition. “Pre-trigger samples” defines the number of samples acquired before the trigger condition is met.
If “Multiple level trigger” is set to true, the value of “Pre-trigger samples” is ignored, and the capture starts when the second trigger condition is met.
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Trigger line count: integer range 1 to 32
The trigger lines
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are analysed to find the trigger
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conditions
Trigger mode: “Basic” or “Basic & Edges”
The trigger lines
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are analysed to find the trigger
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conditions
There are two possible 2 trigger modes:
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Note
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: Basic & Edges provides more trigger flexibility, but requires
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more logic resources for trigger implementation
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Multiple level trigger: “Enable” or “Disable”
When “Capture mode” is set to “Pre-trigger” the user can define a two-level trigger condition. The analyzer analyser will search first for the first level trigger condition, before searching for the second level and final trigger condition and start the data capture. For this, the “Multiple level trigger” must be set to true, and the “First level trigger value” must be defined by the user.
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A VHDL encrypted file is then generated. A header in clear VHDL (not encrypted) is available. This header appears as comments. It can be used for the component declaration when instantiating the NxScope IP Core in the design to be analyzedanalysed.
NxScope Capture Tools
After compiling the design, the user must send the bitstream to the FPGA and then launch the data capture.
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Once the data has been captured, an ACSII file is generated (.TXT or .VCD). The results can be then analyzed analysed in the ModelSim waveform viewer (.TXT result file), with a simple testbench or with the free GTKWave waveform display software using the .VCD result file.
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As mentioned previously the ModelSim waveform viewer can be used to visualize and analyze analyse the captured results (.TXT result file).
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The user can then set its own waveform settings.
Open the .VCD result file with GTKWave and view/
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analyse the captured results
GTKWave is a free waveform display software. It allows to display the waveform of signals that are stored in .VCD format.
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