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See Impulse (Graphical User Interface) to create a project with the impulse user interface
See Nxpython specification to create a project with the nxpython command-line interface
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Synthesis
Synthesis translates the design hardware description into a gate-level netlist using FPGA resources.
You can run the Synthesise step of the design flow in both Impulse and the nxpython environments (please refer to sections Synthesise and synthesizesynthesise().
Place and Route
The Place and Route steps are performed on the synthesized synthesised design generated in the previous step.
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Static Timing Analysis (STA) can be performed by using its Timing Analyzer analyser tool to analyzeanalyse, debug, and validate the timing performance of the design.
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Impulse can load a project at each flow milestone called Synthesize synthesise, Place & Route with their associated flow steps as long as a file at .nym format has been generated during flow execution of the corresponding step.
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STA Manager gives the possibility to schedule - after Synthesis, Place or Route steps - or directly launch a Static Timing Analysis regarding certain parameters such as the requested condition case scenario, the maximum number of violating paths or the maximum slack upon analyzeanalyse:
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d. IP
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Importing an external set of pads assignment can only be performed after Synthesize synthesise flow execution and before the execution of first step of Place flow. Otherwise, the tool will provide automatic pad configuration to execute Place & Route flow steps.
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general.log | contains all messages printed during the execution of nxmap steps: full tool log. |
synthesizesynthesise.log | contains all messages printed during the execution of the two synthesis steps. These information are also generated into the general.log file. |
place.log | contains all messages printed during the execution of the five placement steps. These information are also generated into the general.log file. |
route.log | contains all messages printed during the execution of the three routing steps. These information are also generated into the general.log file. |
bitstream.log | contains all messages printed during the execution of the bitstream generation step. These information are also generated into the general.log file. |
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nxpython lists in latches.rpt all latch elements synthesized synthesised during flow execution.
Maplogic report
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The floorplan view into Impulse allows graphical inspection through the synthesized synthesised design with a set of specific commands.
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Show instances color colour allows to modify the colors of design instances, also according instance color colour for logical elements constrained in regions to the same color colour of the corresponding regions
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outside existing regions, the logic is scattered into the fabric (identified as top level element with ‘~') and a right click on this gives access to General and Region '~’ menus
General allows to Edit Fabric dimensions inside which logic should be mapped, Create a Region or Create an Obstruction from scratch
Region ‘~’ allows to edit the dimensions of the top level '~’ region of the design, which represents by default the top level design and the logic inside it which is not constrained within user-defined regions
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Right Click → Select General → Edit Fabric to open the labelled editor and edit the dimensions of the fabric '~' as well as the relative focus point in order to modify the size of the matrix used by default to map resources
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Right Click → Select General → Create obstruction to open the labelled editor and create a user-defined obstruction with desired coordinates
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If coordinates are missing or out of bounds, Impulse will |
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display a red warning message and |
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the obstruction creation will not be able to |
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be validated until the coordinates are corrected |
Right Click → Select General → Create Region to open the labelled editor and create a user-defined region with:
Your desired Name
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and colour tone
Ability to choose if the region is exclusive or not
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Aperture coordinates, to define the location and size of the region
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Anchor coordinates, for the focus point
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Note: Anchor coordinates are placed in the middle of the fabric by default when
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Inherit focus checkbox is
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ticked
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→ click on accept when the destination region is selected and you will observe in the floorplan that the logic instances color colour identification will be modified to match the destination region color
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The Logic Cone Manager provides worstcase, bestcase and typical conditions choice through a scrolling button.
Reported elements to be analyze analyse for the selected instance can be parsed by a desired type of pin : Clock, Load or Reset.
Useful options to use within the Logic Cone Manager are Depth and Max Depth arguments, which allow to extend from one selected elements analyzed analysed with their accumulated timing values to several level of logical instances to be shown and included in the graph. That way, a user can trace back multiple layers of instances back and forward to determine complex dependencies in data paths and how simplification for timing purpose could be useful.
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The size of the aperture can be edited as much as needed (following figure) but user must keep in mind that the current design to be synthesizedsynthesised, placed & routed in the FPGA will have to use a minimum of resources to be correctly mapped. In other words, user can’t define a size for aperture which is too small to map the full design requested otherwise Impulse will generate an error during Place step, preventing the tool to execute all subsequent steps for current design.
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project = createProject()
project.constrainModule('|-> INTERP_x2_20M_to_40M [ INT_20_40 ]', 'INT_20_40_MOD', 'Hard', 5, 4, 2, 3, 'INT_20_40', False)
project.constrainModule('|-> INTERP_x2_40M_to_80M [ INT_40_80 ]', 'INT_40_80_MOD', 'Hard', 7, 4, 2, 3, 'INT_40_80', False)
project.constrainModule('|-> SRL_MEM_SYMMETRY_EVEN(X834F2609) [ FIR_MF|MEM|EVEN.MLT.NR[0].FIRST.FIRST_EVEN ]', 'FIRST_EVEN_MOD', 'Hard', 1, 10, 1, 1, 'FIRST_EV_1_R', False)
project.constrainModule('|-> SRL_MEM_SYMMETRY_EVEN(X30E78A1F) [ FIR_MF|MEM|EVEN.MLT.NR[1].OTHE.OTH_EVEN ]', 'OTH_EV_1', 'Hard', 2, 10, 1, 1, 'OTH_EV_1_R', False)
project.constrainModule('|-> nx#NX_DSP_SPLIT(X2C70EFCA) [ FIR_MF|GEN_DSP[0].DSP|G_INST.DSP ]', 'DSP_MOD_1’, Hard', 1, 8, 1, 1, 'DSP_SPLIT_1’, False)
project.constrainModule('|-> nx#NX_DSP_SPLIT(X2C70EFCA) [ FIR_MF|GEN_DSP[2].DSP|G_INST.DSP ]', 'DSP_MOD_3', 'Soft', 3, 8, 1, 2, 'DSP_SPLIT_3', True )
project.save('/rtl/native.nym')
project.synthesizesynthesise():
project.save('/rtl/synthesizedsynthesised.nym') |
Once Synthesize synthesise step of the flow is executed using region constraints from constrainModule() commands, hierarchy.rpt provides useful information to check preliminary constraints as written by user before flow implementation - specified by Unused (Not yet assigned) - and after usage by the tool for execution.
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And finally, a look a floorplan panel of Impulse offers visual glimpse on how region constraints with the associated logic instances placed inside are placed in delimited resources with color colour codes:
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project = createProject()
project.constrainPath(['i_cpt_0|s_cpt_out_reg*'],['i_cpt_1|s_cpt_out_reg*'],'cpt0_to_1_module','Soft',9,6,2,3,'cpt0_to_1_region',False)
project.constrainPath(['i_cpt_1|s_cpt_out_reg*'],['i_cpt_2|s_cpt_out_reg*'],'cpt1_to_2_module','Soft',11,6,2,3,'cpt1_to_2_region',True)
project.constrainPath(['i_cpt_2|s_cpt_out_reg[0]'],['i_cpt_3|s_cpt_out_reg[0]'],'cpt2_to_3_module',13,6,2,3,'cpt2_to_3_region')
project.save('/rtl/native.nym')
project.synthesizesynthesise():
project.save('/rtl/synthesizedsynthesised.nym') |
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