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NxScope implements a NanoXplore IP Core generated by the NxCore Generator
The capture process is controlled by JTAG through the ANGIE USB-JTAG adapter via NxBase2 software or the NxBoard GUI
The results are displayed and analysed with either of the following tools:
The ModelSim Waveform Viewer using a simplified testbench to read the TXT file generated by the NxCore generator
The GTKWave Waveform Viewer (free software)
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Note: The NxScope logic analyser is implemented in the FPGA proposed user design. As a result, it makes use of the available logic resources (as available) as of the FPGA unit (e.g. tile logic and RAM blocks. Its implementation must also meet the user’s clock period as well as other potential user constraints.). Make sure all constraints (particularly timing constraints) are met after NxScope is initiated |
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NxScope IP Core comprises 3 main functional blocks:
The Trigger Engine
A configurable moduleA configurable modu module for detecting the trigger conditions to capture samplesThe Capture Unit
A configurable module to store the captured samplesThe JTAG Interface
Activates the trigger engine and transfers captured samples to the workstation through the ANGIE USB-JTAG adapter via NxBase2 software or the NxBoard GUI
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Capture width: 2 to 240 input lines
Capture depth: 2K, 4K, 6K, 8K, 12K, 24K or 48K
Programmable number of samples stored before trigger condition
Optional Windowing windowed capture mode (capture depth is sub-divided in multiple windows)
Optionally stores the trigger pulse
Optionally stores the Window number, if applicable
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Name | Type | Description |
TRIG_ARMED | std_logic | Can be optionally used to monitor the NxScope internal status |
DONE | std_logic | High when the capture is complete. Can be used as status-bit |
FIRST_LEVEL_TRIG_OK | std_logic | High after the first-level trigger condition has been met. Can be used as status-bit to inform about the current state of the analyser when a two-level trigger is selected and, for example, connected to a LED |
CURRENT_CAPTURE_SET | std_logic_vector(3 downto 0) | Available exclusively in “Multiple windows” mode. These 4 bits form a counter that is incremented in single steps whenever a new window capture is started. Beyond 15 windows, the counter wraps around. Can be used as status bits to monitor the progress of the capture windows. |
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Once the data has been captured, an ACSII file is generated ( in TXT or VCD format).
The results can be analysed in the ModelSim Waveform Viewer (TXT result file), with You can review the TXT results via a simple testbench or with in the ModelSim waveform viewer or the VCD results using the free open source GTKwave waveform viewing software using the VCD result file.
Create a Custom NxScope IP Core
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The NxScope IP Core output goes from low state to high when the first trigger condition has been met.
Trigger value
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When “Trigger mode” is set to “Basic”, each trigger line will be compared to the following possible values: ‘0’, ‘1’ or ‘Ignore’
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Launch Sample Capture with NxBase2
Use NxBase2nxbase2_cli to run the following commands:
Load the bitstream:
Code Block >> NxBase2nxbase2_cli –s /bitstream_path/bitstream_name.nxb
Launch a capture*:
For a (ModelSIM) TXT file
Code Block >> NxScopenxscope capture dump.txt 50E6
For (GTKWave) VCD file
Code Block >> NxScopenxscope capture dump.vcd 50E6
*Where 50E6 is the frequency of the sample clock for the design (50 * 10**6 = 50 MHz in this case).
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.txt: preferred format for waveform display on ModelSim/QuestaSim
.vcd: preferred format for waveform display on GTKwave – free software
NxScope
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Capture Sequence
After configuring the FPGA with the bitstream containing the NxScope IP Core and before launching the NxScope capture command, the “DONE” and ‘TRIG_ARMED” output pins of the NxScope IP Core are low. The IP Core is waiting for a command.
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