This document is intended to guide users of NanoXplore NXmap Impulse software through all the steps involved in the design flow and the options available in NanoXplore design suite:

nxmap impulse is a graphical interface that allows user to view and compile an existing project.
nxpython is a wrapper around Python executable that allows user to control nxmap impulse software as a wrapper. It fully supports Python syntax, structures and external modules.
The creation of a new project can be performed with both nxmap impulse and nxpython tools.

All commands described in this document for NXpython can be applied to the provided VHDL examples in example folder.

Package description

The provided nXmap impulse archive contains the following directories:

bin folder contains binary files for each supported Linux distribution
doc folder contains documentation files in pdf format
example folder contains several examples of different projects with design sources in VHDL
lib64 folder contains dynamic libraries and Python modules for each supported Linux distribution and associated Python version
share folder contains additional files (vhdl libraries, simulation libraries, etc...)

Installation

To install nxmapimpulse, the user needs to unpack nxmapimpulse-VERSION.tar.gz file into the installation directory (e.g. /opt/NanoXplore) using the following command:

Code Block
$> tar xzf nxmapimpulse-VERSION.tar.gz -C /opt/NanoXplore

...

Code Block
$> /opt/NanoXplore/NXmap3impulse/VERSION/bin/nxpython

To use the nanoxmap module in python, user must first call the following command in nxpython:

Code Block

language	py

from nxmapnxpython import *

Anchor
nxpythonspec
nxpythonspec
Nxpython specification

...

This chapter presents the general purpose commands. These commands do not need any object to be called as they are directly defined in the nxmap impulse module.

createProject([workingDirectory])

...

This function is used to print an error message in the nxmap impulse output. This includes terminal output and log file if set. An error message is prefixed by ERROR string so it can be easily found.

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This function is used to print a remark message in the nxmap impulse output. This includes terminal output and log file if set. An error message is prefixed by REMARK string so it can be easily found.

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This function is used to print a message in the nxmap impulse output. This includes terminal output and log file if set. When no message is given, method prints a new line in the nxmap impulse output.

Arguments:

Name	Type	Description
message	string	message to print

...

This function is used to print a warning message in the nxmap impulse output. This includes terminal output and log file if set. A warning message is prefixed by WARNING string so it can be easily found.

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The idea is to offer the possibility to the user to reuse the result of an nxmap impulse flow as an IP in a top design.

...

The user can then reuse the result of this first flow in another design. named top, which instanciates the IP entity several times.

Nxmap Impulse will use the result of synthesis and place from the first flow and replicate then in the top flow

...

Note

It can be useful “*” in getModels and getInstances method as following:

project.addMappingDirective(getModels('*myFifo*'), 'RAM', 'RAM')

The first "*" is used because your model is defined in a VHD library.

The second "*" is used because your "myFifo" model uses some generic map and thus is renamed to myFifo(#id) by nxmapimpulse.

Note
Mapping a RAM into DFF is only available with getModels but not getInstances.

...

LVCMOS (Default)
LVDS
LVDS_STR
SSTL
HSTL

Note
NXmap3 Impulse only supports ‘Undefined’ value for drive option when ‘LVDS’ standard is selected.

...

If “pads” are not configured of configured incompletely, nxmap impulse will randomly place non assigned ports on the FPGA

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This method is used to create an obstruction object which will be removed from nxmap impulse resources for Place & Route steps.

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developCKGs() allows the user to create generated clocks for CKGs' output pins. For example, before activating a generated clock whose base clock is driven by a WFG, user needs to launch this method for generating the base clock.

Without this method, nxmap impulse automatically derives a clock on each output of the CKGs after activating all the given timing constraints.

...

Code Block
Display after destruction Traceback (most recent call last): File "test.py", line 22, in <module> project.display() nxmapimpulse.error: Invalid Request: Obsolete object

...

This method is used to open current project in nxmap impulse graphic user interface. It can be called several times from the same Python script.

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This method is used to export the synthesized design to an IPCore. An IPCOre is a HDL description (at NX components level) that can be given as part of new source design to nxmap impulse.

The export is different from the save() method as it is done during the second step of synthesis.

...

Name	Description
coreName	the name of the top entity in the IPCore (default is top cell name during synthesis)
obfuscate	if set to ‘Yes’, the generated code is obfuscated (default is ‘No’)
encrypt	used to encrypt the generated file using IEEE P1735 standard. If set to ‘None’, the file is not encrypted, otherwise it is and the value corresponds to the software targeted: ‘NX’: to reuse file in nxmap impulse ‘MGC’: to reuse file in QuestaSim ‘All’: to reuse the file in nxmap impulse and / or QuestaSim
author	author information used in the encrypted file header
license	license information used in the encrypted file header

...

This method is used to load a previously saved project from disk. The input format (file extension) must be .nym (nxmap impulse archive).

Arguments:

Name	Type	Description
file	string	nxmap impulse archive file (extension must be .nym).

...

Name	Name of the HDL port
Direction	Direction of the port (can be input, output or inout)
Location	Pad location associated to the port (can be set by the user or automatically set by nxmap impulse)
Type	Type of the associated pad
SlewRate	Slew rate value of the associated pad
InputDelayLine	Input delay line of the associated pad
OutputDelayLine	Output delay line of the associated pad
Differential	True if the associated pad is in differential mode
Turbo	True if the associated pad is in turbo mode

...

This method is used to save the current project into a nxmap impulse archive (.nym), a design netlist (.v or .vhd) or to generate a sdf file containing delays of the design supporting bestcase, worstcase and typical scenarios.

...

Code Block

language	py

project = createProject()
project.setDescription('NXmapImpulse project for training')

setDirectory(directory)

...

Name

Default

Description

'Autosave'

'Yes'

Enable automatic protect save after each flow step.

'BypassingEffort'

'Medium'

Specify the DFF load and reset spreading level into the low-skew network (can be 'Low', 'Medium' or 'High'):

Low: all Load and Resetare sent in low skew

Medium: NXmap Impulse choose an effective balance

High: all Load and Reset are routed in common parts ( high routing constraint)

'CMICLatency'

'0'

Additional delay between 2 CMIC scans.

Expressed in number of BSM clock cycles.

'CongestionEffort'

'High'

Specify the routing resources limit per tile (can be 'Low', 'Medium' or 'High'):

Low : less routing constraints but may need further more tiles and CGBs
Medium : balanced routing constraints but may need more tiles and CGBs
High : all routing resources

'Dynamic'

'No'

Refresh view while algorithms are running.

'DefaultFSMEncoding'

'OneHot'

Default encoding of finite state machine (can be 'OneHot', 'OneHotSafe', 'OneHotSafeExtra' or 'Binary'):

OneHot: only one bit changes per state
OneHotSafe: detects invalid state where all bits are ‘0’ and returns to others case
OneHotSafeExtra: detects invalid combinations where there is more than one bit to ‘1’ at a time

'DefaultRAMMapping'

'AUTO'

Default mapping of RAM (can be 'AUTO', 'RF', 'RAM' or 'RAM_ECC').

'DefaultROMMapping'

'AUTO'

Default mapping of ROM (can be 'AUTO', 'LUT', 'RF', 'RAM' or 'RAM_ECC').

'DensityEffort'

'Low'

Specify the instance resources allowed per tile (can be 'Low', 'Medium' or 'High'):

Low: less resources (less routing constraints but may need more tiles and CGBs): 70% is allowed
Medium: well suited resources: 80% is allowed
High: more resources (more routing constraints): 90% is allowed

'DisableAdderBasicMerge'

'No'

Disable carry optimization around adders and subtractors.

'DisableAdderTreeOptimization'

'No'

Disable adder mux reordering and adder tree balancing.

'DisableAdderTrivialRemoval'

'No'

Disable simplification of adder that could fit in 1 or 2 LUTs.

'DisableAssertionChecking'

'No'

Deactivate VHDL assertions.

'DisableDSPAluOperator'

'No'

Disable merge of ALU within inferred DSP.

'DisableDSPFullRecognition'

'No'

Disable inference of DSP.

'DisableDSPPreOperator'

'No'

Disable merge of pre-operator within inferred DSP.

'DisableDSPRegisters'

'No'

Disable merge of registers within inferred DSP.

'DisableRegisterMergeInDspForAdd'

‘No’

Disable merge of registers in DSP when used as adder

'DisableKeepPortOrdering'

'No'

Disable keep port ordering used in source files when generating HDL netlists.

'DisableLoadAndResetBypass'

'No'

Disable load and reset signal bypass on DFF.

'DisableRAMAlternateForm'

'No'

Disable recognition of registered address read port.

'DisableROMFullLutRecognition'

'No'

Disable merge of ROM recognized as LUT with logic.

'DisableRAMRegisters'

'No'

Disable merge of registers within inferred RAM.

‘ExhaustiveBitstream’

‘No’

Can be used to force generation of all configurations and contexts in bitstream (can be ‘No’, ‘Config’, ‘Context’ or ‘ConfigContext’).

'GenerateBitstreamCMIC'

'No'

Generate bitstream with CMIC.

‘InitializeContext’

'No'

Initialize all DFF, RFB and RAM of the chip.

It increases the bitstream size.

'IgnoreRAMFlashClear'

'No'

Do not output error when recognizing a RAM with flash clear.

'ManageAsynchronousReadPort'

'No'

If 'Yes', detect asynchronous read port in memories and repair it in synchronous read port. The read port receive the reversed write clock. It can slow down the design and sometimes may cause invalid behavior.

'ManageUnconnectedOutputs'

'Error'

Undriven outputs of HDL modules are treated as 'Error', 'Ground' or 'Power'.

'ManageUnconnectedSignals'

'Error'

Undriven internal signals of HDL modules are treated as 'Error', 'Ground' or 'Power'.

'ManageUninitializedLoops'

'No'

Remove reset-less looped DFF causing extra-mapping and 'X' values in simulation (can be 'No', 'Power, ''Ground').

'MappingEffort'

'Low'

Effort for an optimized mapping in terms of primitive instance merging and simplification (can be 'Low', 'Medium' or 'High'):

Low: almost no optimization
Medium: balanced optimizations
High: almost all optimizations

'MaxRegisterCount'

'2500'

Maximum number of registers handled per HDL module (not the whole design) by the synthesizer.

‘OptimizedMux’

‘Yes’

If set to 'Yes', nxmap impulse will identify and convert every mux in the corresponding optimized 4-LUT structure.

'PartitioningEffort'

'Medium'

Define the size of the netlist subset which will be further optimized for timing goals achievement (can be 'Low', 'Medium' or 'High') :

Low: small part
Medium: medium part
· High: huge part

Info
Option is activated only if TimingDriven option is enabled.

'PolishingEffort'

'Medium'

It allows to regenerate locally a signal in TILE which in normal way should be provide by an others TILE in order to reduce utilization of routing resources.

Low: deactivate
Medium: can replicate LUT
High: can replicate LUT and DFF

'ReadyOffWithSoftReset'

‘Yes’

Only available for NG-ULTRA variant.

It links the ready falling edge to soft reset enabling during the power off reset sequence.

‘ReplicationApproval’

‘Yes’

Allow replication in a close TILE if not possible in the current TILE.

No: Do not allow replication
Yes: Allow replication

'RoutingEffort'

'Medium'

Routing Optimization level in terms of routing instances (can be 'Low', 'Medium' or 'High'):

Low: no optimization
Medium: balanced optimizations
High: further optimizations but time consuming

‘SaveTiming'

‘No’

Save STA in .nym project files

No: STA is not saved in project files
Yes: STA is saved in project files

‘Seed’

‘1789’

Seed for placing algorithm start. Depending on the seed, instances are created in a different order and placed so.

Can be used in order to generate several Place & Route with the same synthesized project.

'SetRunAfterContext'

‘No’

Indicate the sequence in the bitstream between run (routing instances enable) and context (initialization values for DFF, RFB, RAM).

No: Run is set before Context
Yes: Run is set after Context

‘SimplifyRegions’

‘Yes’

Clear module and region database:

delete modules without instance
delete regions without module
merge identical regions

‘SytemOutputDriven’

'No'

Increase placing close to the ring for instances communicating with.

No: No priority for these instances in algorithm
Yes: Allow priority for these instances in alogrithm

'TimingEffort'

‘High’

Indicates level of iterations for TimingDriven algorithm.

Low: no iteration
Medium: a few iteration
High: more iterations

Info
Option is activated only if TimingDriven option is enabled.

Note
For heavy designs, runtime can increase drastically depending on number of iterations.

'UnusedPads'

'Floating'

State in which the pads must be set when not used. Values can be 'Floating','WeakPullUp', 'WeakPullDown'. Note that when the state is different from 'floating', all the pads are serialized in the bitstream.

Note that ‘WeakPulldown’ value is not available on NX1H35S component.

‘VariantAwareSynthesis’

‘Yes’

If set to ‘Yes’ synthesis will automatically map to equivalent resource when specific resource is depleted. For example using DSP when there are no more CY available (can be ‘Yes’ or ‘No’).

...

The list of all the instances identified by nxmap impulse from your design is available in the log file operators.rpt in logs directory.

It is also possible to get the list of all the instances identified by nxmap impulse using “*” expression as instance name in getInstances method, as following:

project.addMappingDirective(getInstances('*'), 'RAM', 'RAM')

This way, you will see all the available instances in the general.log file in logs directory.

...

It can be useful to use "*" in getModels method as following:

project.addMappingDirective(getModels('*myFifo*'), 'RAM', 'RAM')

The first "*" is used because your model is defined in a VHD library.

The second "*" is used because your "myFifo" model uses some generic map and thus is renamed to myFifo(#id) by nxmapimpulse.

The list of all the models identified by nxmap impulse from your design is available in the log file operators.rpt in logs directory.

It is also possible to get the list of all the models identified by nxmap impulse using “*” expression as model name in getModels method, as following:

project.addMappingDirective(getModels('*'), 'RAM', 'RAM')

This way, you will see all the available models in the general.log file in logs directory.

...

Code Block

breakoutMode	wide
language	py

import os
import sys
from nxmapnxpython import *

dir = os.path.dirname(os.path.realpath(__file__))
project = createProject(dir)
project.setVariantName('NG-MEDIUM')
project.setTopCellName('WOB_MAC_FIR')

project.addFiles([
   'src/src_WOBUL/SUB_ADD.vhd', 
   'src/src_WOBUL/SIN_TAB_8K.vhd', 
   'src/src_WOBUL/SIN_TAB_8K_360.vhd', 
   'src/src_WOBUL/WOBUL.vhd', 
   ])

project.addFiles([
   'src/src_MAC_FIR/MULTI_MAC_FIR_Package.vhd', 
   'src/src_MAC_FIR/CLKGEN.vhd', 
   'src/src_MAC_FIR/SRL_MEM_SYMMETRY_EVEN.vhd', 
   'src/src_MAC_FIR/SRL_MEM_SYMMETRY_ODD.vhd', 
   'src/src_MAC_FIR/TOP_SRL_MEM_MULTI_SYMMETRY.vhd', 
   'src/src_MAC_FIR/MAC_CAPT.vhd', 
   'src/src_MAC_FIR/ADDER_TREE.vhd', 
   'src/src_MAC_FIR/TOP_MAC_FIR.vhd', 
   ])

project.setOptions({
   'MappingEffort': 'High', #can be replaced by  'Medium' or  'Low'
   })

ioBanks = { 
   'IOB12'  : {'voltage': '2.5'},
   'IOB10'  : {'voltage': '1.8'},
   'IOB01'  : {'voltage': '2.5'},
   'IOB00'  : {'voltage': '2.5'},
     }

pads = {
      'CLK25M_IN'  : {'location': 'IOB12_D09P', 'standard': 'LVCMOS', 'drive' :'4mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'RST_PIN'    : {'location': 'IOB10_D12N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},          
      'TRIG_IMMEDIATE_EXT'  : {'location': 'IOB10_D07N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1}, 

      'LEDS_N_8'       : {'location': 'IOB01_D02N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[2]'  : {'location': 'IOB01_D06P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[1]'  : {'location': 'IOB01_D06N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[0]'  : {'location': 'IOB01_D05P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},

      'LEDS_N_4'  : {'location': 'IOB01_D05N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_3'  : {'location': 'IOB00_D03P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_2'  : {'location': 'IOB00_D03N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_1'  : {'location': 'IOB00_D01P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
   }
project.addPads(pads)

#clock constraint
project.createClock(getClockNet('CLK25M_IN'), 'CLK25M_IN', 40000, 0, 20000)

#Create regions ton confine logic
project.addModule('*WOBUL', 'WOBU', 'WOBU-%')
project.createRegion('WOBUR', 1, 2,  2, 4, False)
project.confineModule('WOBU-1', 'WOBUR')

project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[[1-8]].OTHE.OTH_EVEN', 'OTH_EVEN-%')
project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[0].FIRST.FIRST_EVEN', 'FIRST_EVEN-%')
project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[9].CENT.CENTER_EVEN', 'CENTER_EVEN-%')

project.createRegion('OTH_EV_1_R', 2, 10, 2, 10, False)
project.confineModule('OTH_EVEN-1', 'OTH_EV_1_R')
project.createRegion('OTH_EV_2_R', 3, 10, 3, 10, False)
project.confineModule('OTH_EVEN-2', 'OTH_EV_2_R')
project.createRegion('OTH_EV_3_R', 4, 10, 4, 10, False)
project.confineModule('OTH_EVEN-3', 'OTH_EV_3_R')
project.createRegion('OTH_EV_4_R', 5, 10, 5, 10, False)
project.confineModule('OTH_EVEN-4', 'OTH_EV_4_R')

project.createRegion('OTH_EV_5_R', 6, 10, 6, 10, False)
project.confineModule('OTH_EVEN-5', 'OTH_EV_5_R')
project.createRegion('OTH_EV_6_R', 7, 10, 7, 10, False)
project.confineModule('OTH_EVEN-6', 'OTH_EV_6_R')
project.createRegion('OTH_EV_7_R', 8, 10, 8, 10, False)
project.confineModule('OTH_EVEN-7', 'OTH_EV_7_R')
project.createRegion('OTH_EV_8_R', 9, 10, 9, 10, False)
project.confineModule('OTH_EVEN-8', 'OTH_EV_8_R')
project.createRegion('FIRST_EV_1_R', 1, 10, 1, 10, False)
project.confineModule('FIRST_EVEN-1', 'FIRST_EV_1_R')
project.createRegion('CENT_EV_R', 10, 10, 10, 10, False)
project.confineModule('CENTER_EVEN-1', 'CENT_EV_R')

# Synth                 FIR_MF_GEN_DSP_0_DSP_G_INST_DSP_DSP_INST
# Routed              FIR_MF_GEN_DSP_0_DSP_G_INST_DSP_DSP_INST
# NXmapImpulse GUI      FIR_MF|GEN_DSP_0_DSP|G_INST.DSP|DSP_INST
project.addDSPLocation('FIR_MF|GEN_DSP[0].DSP|G_INST.DSP|DSP_INST', 'CGB[1x8]:L') 
project.addDSPLocation('FIR_MF|GEN_DSP[1].DSP|G_INST.DSP|DSP_INST', 'CGB[1x8]:R') 
project.addDSPLocation('FIR_MF|GEN_DSP[2].DSP|G_INST.DSP|DSP_INST', 'CGB[2x8]:L') 
project.addDSPLocation('FIR_MF|GEN_DSP[3].DSP|G_INST.DSP|DSP_INST', 'CGB[2x8]:R') 

# i_WOB_TABLE_ROM_TAB_SINUS_ram0_0_0_0
#project.addRAMLocation('*SINUS*', 'CGB[3x8]')
project.addRAMLocation('WOBU|TABLE|ROM_TAB|SINUS|ram0_0_0_0', 'CGB[1x4]') 
project.addRAMLocation('GEN_SCOP.SCOP|MEASUR|GEN_PRE_TRG*MEM|ram0_0_0_0', 'CGB[2x4]') 
project.addRAMLocation('GEN_SCOP.SCOP|MEASUR|GEN_PRE_TRG*MEM|ram0_0_1_0', 'CGB[3x4]') 
project.addRAMLocation('GEN_SCOP.SCOP|MEASUR|GEN_PRE_TRG*MEM|ram0_0_2_0', 'CGB[4x4]') 
project.addRAMLocation('GEN_SCOP.SCOP|MEASUR|GEN_PRE_TRG*MEM|ram0_0_3_0', 'CGB[5x4]') 

#false paths declarations
#project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[*'), getRegisters('FIR_MF|SUM|PRESUM_reg[*'))
#project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][*'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][0]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][1]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][2]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][2]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][4]'))

project.save('native.nym')               
                                         
if not project.synthesize():             
    sys.exit(1)                                                               
project.save('WMFS_Cores_synth.vhd')        
            
if not project.place():                  
    sys.exit(1)                          
project.save('WMFS_Cores_placed.nym')                                         

if not project.route():                  
    sys.exit(1)                          
                                         
project.reportPorts()                    
project.reportInstances()                
                                                                                     
project.save('WMFS_Cores_routed.nym')
project.save('WMFS_Cores_routed.vhd')

analyzer = project.createAnalyzer()
analyzer.launch({
   'conditions': 'worstcase',           # 'typical', 'worstcase', or 'bestcase'
#   'maximumSlack': 10000,
   'searchPathsLimit': 100
   }) 

#bitstream generation
project.generateBitstream('WMFS_Cores.nxb')

print( 'Errors: ', getErrorCount())
print( 'Warnings: ', getWarningCount())

...

Timing path is the connection between two certain nodes in the design i.e. connection between primary input and output ports, connection between primary input ports/clock pins and data input pins of the sequential elements, and connection between intermediate clock pins and primary output ports.

Data delay

In nxmap impulse, data delay is the delay of a timing path. For example, the delay between the launch edge of the clock at the source register and data input pin of the destination register. In following picture, the path for the data delay between source register DFF1 and destination register DFF2 is shown in blue.

...

Hold time is the minimum amount of time required for a signal to retain its value after the clock transition. In nxmap impulse, the analysis of setup/hold time is performed in order to calculate the data arrival time which will be explained shortly.

...

Similarly, removal time is the minimum amount of time for an asynchronous signal to be held stable before its de-assertion after the previous active clock edge. The removal time calculation corresponds to the hold time calculation but for the asynchronous signals.

Timing domain

In nxmap impulse, the term ‘domain’ is used to define a group of certain timing paths. As mentioned earlier, the timing paths include the connection between primary input and output ports, connection between primary input ports/clock pins and data input pins of the sequential elements, and connection between intermediate clock pins and primary output ports.

...

Anchor

	Figure12
	Figure12

...

Data arrival time

In nxmap impulse, data arrival time includes the overall data delay, clock skew and setup/hold time (recovery/removal) for a critical timing path in a domain. Based on the setup/hold verification, data arrival time can be either maximum or minimum. In both cases, data arrival time is calculated as follows:

...

Anchor

	Figure16
	Figure16

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Slack calculation

In nxmap impulse, setup/recovery slack corresponds to the difference between maximum setup/recovery relationship and maximum data arrival time whereas hold/removal slack corresponds to the difference between minimum data arrival and minimum hold/removal relationship.

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timingreports
timingreports
Timing reports

In nxmap impulse and nxpython, timing analyzer generates a set of reports presenting respectively the summary of analysis, critical paths of each domain, and violation information. All the timing reports are automatically saved in files (.timing) in ‘logs’ directory after a successful analyzing of the routed design.

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The following table shows the revision history of the NXmap3 user manual datasheetImpulse_NXpython specification document:

Date	Version	Revision
20202022-0412-0215	31.0.1	Initial draft datasheet.
2020-12-18	3.0.3	Various corrections for IO names to respect ballout syntaxe now used in NXmap3 software.
2021-04-02	3.0.4	constrainPath() and constrainModule() descriptions introduced. Updated addPad() description to clarify the applications of several options and provide trade-off examples.
2021-07-23	3.0.5	addMappingDirective() supports the mapping of ADD into LUT. addPad() additional precisions: termination specified in Ohms within a range 30 to 80 weakTermination values ‘None’ and ‘PullUp’ not allowed for NG-MEDIUM setLogDirectory() function implemented. addFile() supports VHDL_93, VERILOG_95, VERILOG_2K language identifiers for synthesis through NXmap3. bestcase, worstcase and typical scenarios supported for sdf file generation. Overview of expected expression (full path, wildcard or regular expressions or for NXpython methods) is provided in section 5.2.2 List of NXpython methods expecting expressions.

Versions Compared

Old Version 17

New Version 18

Key

Package description

Installation

Anchor
nxpythonspec
nxpythonspec
Nxpython specification

createProject([workingDirectory])

setDirectory(directory)

Data delay

Timing domain

Data arrival time

Slack calculation

Anchor
timingreports
timingreports
Timing reports

Page Comparison

Versions Compared

Old Version 17

New Version 18

Key

Package description

Installation

AnchornxpythonspecnxpythonspecNxpython specification

createProject([workingDirectory])

setDirectory(directory)

Data delay

Timing domain

Data arrival time

Slack calculation

AnchortimingreportstimingreportsTiming reports

Anchor
nxpythonspec
nxpythonspec
Nxpython specification

Anchor
timingreports
timingreports
Timing reports