Table of Content

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This document aims at giving guidelines on how to use the provided NX components in VHDL source code for NXmap3Impulse. Its purpose is to explain how to correctly instantiate the different supported NX components provided by NanoXplore for NXmap3 Impulse synthesis and implementation tools.

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The NX_CKS can be used exclusively by instantiation. The current version of NXmap Impulse does not yet support inference for this device.

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Internal 200 MHz oscillator (precision and stability over PVT around 10%)
- Can be used as auxiliary clock
- In addition, this oscillator is used by NXmap Impulse to calibrate the programmable delays available in :
  - PLL feedback path
  - WFG (to delay the clocks)
  - IOs input, output and tri-state command paths (complex IO banks only)

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Ports

Direction

Type

Description

REF

In

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

FBK

In

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

VCO

Out

std_logic

VCO output : Fvco = fbk_intdiv * 2**(fbk_div_on - ref_div_on + 1) * clk_ref_freq

Connectivity: WFG inputs

D1…D3

Out

std_logic

Divided clocks. Fvco frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128

Important note: D1, D2 and D3 outputs are reset while PLL RDY is not asserted.

Connectivity: WFG inputs

OSC

Out

std_logic

Internal 200 MHz oscilator

Connectivity :WFG inputs, delay calibration system

RDY

Out

std_logic

High when PLL is locked

Connectivity: RDY inputs of WFGs, fabric…

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Ports

Direction

Type

Description

REF

In

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

FBK

In

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

R

In

std_logic

Active high Reset input. Must be activated when REF input frequency changes to force a re-locking process of the PLL

VCO

Out

std_logic

VCO output:

- Internal feedback: Fvco = 2 * (fbk_intdiv + 2) * clk_ref_freq / (ref_intdiv + 1)

- External feedback: Fvco = (pattern_end + 1) / n_sim_pat * clk_ref_freq / (ref_intdiv + 1)

Where n_sim_pat is the number of similar patterns sequence found in pattern_end+1 MSB bits of pattern.

REFO

Out

std_logic

Output of the REFerence divider. The division factor is set by the generic “ref_intdiv”

LDFO

Out

std_logic

Output of the FBK_INTDIV divider. The division factor is set by the generic ‘fbk_intdiv”

DIVP1

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp1”

DIVP2

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp2”

DIVP3

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp3o2”

DIVO1

Out

std_logic

This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divouto1”

DIVO2

Out

std_logic

This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divoutp3o2”

OSC

Out

std_logic

200 MHz coming from 400MHz internal oscilator

Connectivity :WFG inputs, delay calibration engine

PLL_LOCKED

Out

std_logic

High when PLL is locked

Connectivity: RDY inputs of WFGs, fabric…

CAL_LOCKED

Out

std_logic

High when the automatic calibration procedure of the current FPGA quarte area is complete

Connectivity: fabric

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Core logic

NX_CY (!)

Note
on nxmap3Impulse, the NX_CY primitive includes only the dedicated arithmetic logic, excluding the Functional Element LUTs and FFs – unlike on nxmap2, where the NX_CY primitive included the FE logic shown in dashed lines.

Description

The NX_ADD component describes a 4-bit adder and carry look ahead circuit. It’s available on the FEs having arithmetic logic capabilities.

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Implement simple decoding functions for Write_Enable or Read_Enable
Address/Data multiplexers to implement time multiplexed two write ports and/or two read ports (not yet supported by NXmapImpulse)

(see NXmap Impulse related notes for more details)

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If the Register_File is used, up to 18 outputs will come from the 64 x 16 RAM array by crossing FE, those registers can be implemented with FE Flip-Flops of the same tile section (16 for Data_out + 2 for ERR and COR outputs)
If the Register_File is partially used (for example as 64 x 8 SDP RAM), the remaining 8 FEs will stay free to implement other unrelated logic functions)

NXmap Impulse support:

The current version of NXmap Impulse supports the implementation of simple decoders on the Write_Enable and Read_Enable commands paths (the Register_File must be instantiated).

LUTs are used as transparent for data inputs as well as read and write addresses (both inference and instantiation).

Future versions of NXmap Impulse will support higher flexibility such as multiplexers and other simple combinatorial function on the data and address input paths.

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