Copyright
All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without consent of NanoXplore.
Introduction
Aim of document
This document is intended to guide users on Training Package testcases.
In order to be more familiar with the Training Package environment, please refer to TrainingPackage_UserManual. For any kind of help, please contact NanoXplore support team at support@nanoxplore.com.
Content
For each testcase of the Training Package, an application note informing about implemented NanoXplore python methods (cf /wiki/spaces/~814749387/pages/48660481) and NanoXplore primitives (cf https://nanoxplore-wiki.atlassian.net/wiki/spaces/SANDBOX/pages/202244165) is provided in this document.
Test plan
List of categories
Testcases are grouped by category depending on the aim of the testcase (python method, primitive, …).
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Attribute: Attributes can be inserted in the design in order to add a constraint on a register, a memory, …
Board: Designs to program NanoXplore evaluation boards (DevKit / BringUp).
Component: Multiple configurations for NanoXplore primitives.
Design: Various types of designs without any specific IP.
Init: Memory initialization
Ip: Designs implementing NanoXplore Ips.
MappingDirective:Directive of elements mapping in NanoXplore primitives.
Pad: Pad configurations.
PlacingConstraint: Constraints for manual placing of NanoXplore primitives.
StaConstraint: Constraintsfor static time analysis.
List of testcases
Hereafter the list of all available testcases for each category:
Attribute:
NxInit
NxPort
NxUse
SynKeep
SynPreserve
Board:
Scope
SwichBlink
ThermalSensor
Component
ClockSwitch
DspConfig
IoConfig
PllConfig
RamConfig
RfbConfig
Service
Soc
WfgConfig
Design
DelayIo
DspCascaded
DspMultAcc
DspTranspose
LowskewManagement
MemInfer
Init
Ram
Ip
CrossDomain
Ddr2Dfi
HsslEsistream
R5AxiMaster
R5AxiSlave
R5Jtag
Serdes
SpacewireLoopback
SpacewireRoadmap
SpacewireRx
MappingDirective
Adder
BlackBox
Memory
Pad
Parameter
Registered
PlacingConstraint
Aperture
ConstrainPath
DspLocation
ExportSites
Focus
Obstruction
PreplaceIp
RamLocation
Region
RingLocation
Site
StaConstraint
ClockGroup
DelayPath
FalsePath
GeneratedClock
InputOutputDelay
ReportPath
Testcase content
Each testcase of this application note contains the following fields:
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Option: Project can be launched with or without an option when launching the python script in order to stress the difference if option is set or not. Please have a look at the https://nanoxplore-wiki.atlassian.net/wiki/spaces/SANDBOX/pages/202244782 for more information.
NanoXmap check: What the user can observe after launching the NanoXmap project.
Simulation check: What the user can observe after launching the Modelsim simulation in case of available simulation environment.
Board check: What the user can observe after programming the bitstream on an DevKit Evaluation Board.
Testcase Description
Attribute
NxInit
Description:
By using nx_init attribute, the user can initialize an inferred memory directly in the design code. It is an alternative way from using the addMemoryInitialization NXpython method in the python script. The syntax is the following one:
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Board check: No board purpose for this testcase.
NxPort
Description:
By using nx_port attribute, the user can add parameters to the design top IOs directly in the design code. It is an alternative way from using the addPad NXpython method in the python script. The syntax is the following one:
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Board check: No board purpose for this testcase.
NxUse
Description:
By using nx_use attribute, the user can add directive for inferred elements directly in the design code. It is an alternative way from using the addMappingDirective NXpython method in the python script. The syntax is the following one:
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Board check: No board purpose for this testcase.
SynKeep
Description:
By using syn_keep attribute, the user can avoid any optimization of a combinatorial signal directly in the design code. syn_keep attribute can be replaced by syn_noprune attribute with exactly the same impact. The syntax is the following one:
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Board check: No board purpose for this testcase.
SynPreserve
Description:
By using syn_preserve attribute, the user can avoid any optimization of a register signal directly in the design code. The syntax is the following one:
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Board check: No board purpose for this testcase.
Board
Scope
Description:
The user can use NxScope IP by implementing it in the design code in order to check signals on a NanoXplore Evaluation board.
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For NG-ULTRA, NxScopeV2 IP Core is used instead of NxScope.
SwitchBlink
Description:
The user can program a NanoXplore Evaluation board (DevKit) with a simple bitstream using switches and LEDs.
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-> Make sure all this check points are OK.
ThermalSensor
Description:
The user can interface with the internal thermal sensor in order to retrieve the junction temperature.
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Board check: Temperature bus is displayed on LEDs.
Component
ClockSwitch
Description:
The user can gate and mux clocks using NanoXplore macro cells in the design code.
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Board check: No board purpose for this testcase.
DspConfig
Description:
The user can make operations using NanoXplore DSP macro cells in the design code.
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Board check: No board purpose for this testcase.
IoConfig
Description:
The user can make operations using NanoXplore IO macro cells in the design code.
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Board check: No board purpose for this testcase.
PllConfig
Description:
The user can generate clocks using NanoXplore PLL macro cells in the design code.
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Board check: No board purpose for this testcase.
RamConfig
Description:
The user can store data using NanoXplore RAM macro cells in the design code.
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Board check: No board purpose for this testcase.
RfbConfig
Description:
The user can store data using NanoXplore Register File macro cells in the design code.
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Board check: No board purpose for this testcase.
Service
Description:
The user can interface with the Bitstream Manager and the Service bank using NanoXplore Service macro cell in the design code.
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Board check: No board purpose for this testcase.
Soc
Description:
The user can interface with the Soc using NanoXplore SOC_INTERFACE macro cell in the design code.
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Board check: No board purpose for this testcase.
WfgConfig
Description:
The user can generate clocks using NanoXplore WFG macro cells in the design code.
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Board check: No board purpose for this testcase.
Design
DelayIo
Description:
The user can drive delays on IO statically or dynamically using NanoXplore macro cells in the design code.
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Board check: No board purpose for this testcase.
DspCascaded
Description:
The user can cascade DSP using NanoXplore DSP macro cells in the design code in order to compute large operations.
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Board check: No board purpose for this testcase.
DspMultAcc
Description:
The user can infer a 12*16+36 operations mapped in DSP.
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Board check: No board purpose for this testcase.
DspTranspose
Description:
The user can implement a 6-tap transpose Finite Impulsion Response filter.
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Board check: No board purpose for this testcase.
LowskewManagement
Description:
The user can interface with the low-skew network through several ways.
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Board check: No board purpose for this testcase.
MemInfer
Description:
The user can infer memories without instantiating NanoXplore macro cells in the design code.
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Board check: No board purpose for this testcase.
Init
Ram
Description:
The user can initialize a memory using the addMemoryInitialization NXpython method in the python script. The syntax is the following one:
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Board check: No board purpose for this testcase.
Ip
CrossDomain
Description:
The user can cross clock domain properly thanks to NanoXplore IP. Implemented IP are:
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Board check: No board purpose for this testcase.
Ddr2Dfi
Description:
The user can interface with a DDR2 memory thanks to the NanoXplore DDR2 DFI IP.
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Board check: Switches and leds allow to control and receive data.
HsslEsistream
Description:
The user can interface with HSSL links thanks to the NanoXplore HSSL macro cell.
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ERROR FLAG deactivated on J15 PIN1
HSSL_CLK at 48MHz on J15 PIN3
ESISTREAM SYNC RX/TX activated on J15 PIN 5
RX_PLL_LOCKED activated on J15 PIN7
PMA RX CLOCK on on J15 PIN13
R5AxiMaster
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
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Board check: No board purpose for this testcase.
R5AxiSlave
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
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Board check: No board purpose for this testcase.
R5Jtag
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
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Board check: No board purpose for this testcase.
Serdes
Description:
The user can send and receive data at high speed thanks to the NanoXplore SERDES macro cells.
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Board check: No board purpose for this testcase.
SpacewireLoopback
Description:
The user can communicate with Spacewire link thanks to the NanoXplore SpaceWire macro cell.
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3- Check data is displayed on LED.
SpacewireRoadmap
Description:
The user can communicate with Spacewire link and Roadmap protocol thanks to the NanoXplore SpaceWire macro cell.
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Board check: No board purpose for this testcase.
SpacewireRx
Description:
The user can retrieve data from a Spacewire Link generating the recovery clock.
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Board check: Data are routed to output LED (falling edge data on LED1 + rising edge data on LED2).
MappingDirective
BlackBox
Description:
The user can declare a component which is a blackbox and map it into the desired NanoXplore macro cell using addBlackbox NXpython method.
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Board check: No board purpose for this testcase.
Memory
Description:
The user can map inferred operations into the desired NanoXplore macro cell using addMappingDirective NXpython method.
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Board check: No board purpose for this testcase.
Operator
Description:
The user can map inferred operations into the desired NanoXplore macro cell using addMappingDirective NXpython method.
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Board check: No board purpose for this testcase.
Pad
Parameter
Description:
The user can configure pads with many parameters using addPad NXpython method.
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Board check: No board purpose for this testcase.
Registered
Description:
The user can map registers, mapped by default in NX_DFF and located in tiles, into NX_DFR located in the pad using addPad NXpython method and registered parameter.
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Board check: No board purpose for this testcase.
PlacingConstraint
Aperture
Description:
The user can focus its design into a defined area using setAperture NXpython method.
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Board check: No board purpose for this testcase.
ConstrainPath
Description:
The user can confine the path between registers in a region using constrainpath NXpython method.
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Board check: No board purpose for this testcase.
DspLocation
Description:
The user can place manually a DSP using addDSPLocation NXpython method.
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Board check: No board purpose for this testcase.
ExportSites
Description:
The user can export placing constraints (setSite, addRAMLocation,…) using exportSites NXpython method.
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Board check: No board purpose for this testcase.
Focus
Description:
The user can focus its design around a point using setFocus NXpython method.
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Board check: No board purpose for this testcase.
Obstruction
Description:
The user can remove regions from available area in the tool using createObstruction NXpython method.
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Board check: No board purpose for this testcase.
PreplaceIp
Description:
The user can preplace an IP and declare IP as a blackbox using addBlackBox NXpython method.
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Board check: No board purpose for this testcase.
RamLocation
Description:
The user can place manually a RAM using addRAMLocation NXpython method.
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Board check: No board purpose for this testcase.
Region
Description:
The user can confine a module in a region using addModule, createRegion and confineModule or directly constrainModule NXpython methods.
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Board check: No board purpose for this testcase.
RingLocation
Description:
The user can place manually PLL and WFG into a CKG using respectively addPLLLocation and addWFGLocation NXpython methods. The method addRingLocation can be used too in both cases.
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Board check: No board purpose for this testcase.
Site
Description:
The user can place manually a register into a tile using setSite NXpython method.
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Board check: No board purpose for this testcase.
StaConstraint
ClockGroup
Description:
The user can specify unrelated clocks using setClockGroup NXpython method or calling SDC constraint.
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Board check: No board purpose for this testcase.
DelayPath
Description:
The user can specify path delays between registers by using addMinDelayPath, addMaxDelayPath and addMulticyclePath NXpython methods or calling SDC constraints.
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Board check: No board purpose for this testcase.
FalsePath
Description:
The user can specify path to be ignored by the STA by using addFalsePath, NXpython method or calling SDC constraint.
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Board check: No board purpose for this testcase.
GeneratedClock
Description:
The user can create a clock directly or specifying its relationship with another clock using respectively createClock and createGenerateClock NXpython method.
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Board check: No board purpose for this testcase.
InputOutputDelay
Description:
The user can apply a minimum and a maximum data arrival time on inputs and outputs using respectively setInputDelay and setOutputDelay NXpython methods.
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Board check: No board purpose for this testcase.
ReportPath
Description:
The user can generate timing reports between two pins or two registers with respectively reportPath or addReportPath and reportTiming or addReportTimingPath NXpython methods.
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