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Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation | |
addBank |
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addBanks |
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addBlackBox |
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addDSPLocation |
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addFalsePath |
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addFile | X |
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addFiles | X |
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addHSSLLocation | |||||||
addIP | X |
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addMappingDirective |
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addMaxDelayPath |
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addMemoryInitialization |
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addMinDelayPath |
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addModule |
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addMulticyclePath |
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addPLLLocation |
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addPad |
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addPads |
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addParameter | X |
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addParameters | X |
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addPin |
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addPins |
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addRAMLocation |
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addRingLocation |
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addRingLocations |
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addVerilogIncludeDirectories | X |
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addVerilogIncludeDirectory | X |
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addVlogDefine | X |
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addVlogDefines | X |
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addWFGLocation |
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adjustAperture |
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applySdcFile | X |
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clearBanks | X |
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clearPLLsclearFabricPrePlaceConstraints | X | ||||||
clearPLLs |
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clearPads X |
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clearPins | X |
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clearWFGs | X |
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confineModule |
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constrainModule |
| X | X |
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constrainPath |
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createAnalyzer |
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createClock |
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createGeneratedClock |
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createObstruction |
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createRegion |
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createSimulator |
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destroy | X |
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destroyObstruction | X |
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destroyRegion | X |
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developCKGs |
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exportAsIPCore | X |
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exportRegions | X |
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exportSites | X |
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generateBitstream |
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generateSTANetlist | X |
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getAnalyzer | X | ||||||
getDirectory | X |
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getErrorCount | X | ||||||
getHierInfo | X | ||||||
getLowskewSignals | X |
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getProject | X | ||||||
getRemarkCount | X | ||||||
getTimingUnit | X |
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getTopCellName | X |
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getVariantName | X |
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getWarningCount | X | ||||||
initRegister |
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limitLowskew |
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listAvailableLocations | X |
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load | X |
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modifyRegion |
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place | X |
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progress | X |
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printError | X | ||||||
printHierInfo | X | ||||||
printRemark | X | ||||||
PrintText | X | ||||||
PrintWarning | X | ||||||
rejectLowskew | X |
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removeFile | X |
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removeFiles | X |
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removeSoftModules | X | ||||||
reportDesignComplexity | X | ||||||
reportInstances | X |
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reportLowskewSignals | X |
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reportPorts | X |
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reportRegions | X |
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reportRegisters | X |
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resetTimingConstraints | X |
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route | X |
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save | X |
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setAnalysisConditions |
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setAperture |
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setCaseAnalysis |
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setClockGroup |
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setDescription | X |
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setDeviceID |
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setDirectory | X |
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setFalsePath |
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setFocus |
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setGCKCount |
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setInputDelay |
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setMaxDelay |
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setMinDelay |
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setMulticyclePath |
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setOption | X |
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setOptions | X |
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setOutputDelay |
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setSite |
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setTopCellName | X |
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setVariantName | X |
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synthesize | X |
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translateAperture |
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...
| Code Block | ||
|---|---|---|
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project = createProject()
project.addBank('IOB0', {'voltage': '2.5'})
project.clearBanks() |
clearFabricPrePlaceConstraints(regionName)
Clears all preplacing constraints for fabric elements. It removes the impact of the following constraints:
setSite
addRAMLocation
addDSPLocation
It gives the ability to clear all Fabric elements constraints and add new ones.
If no argument is set, constraints for the whole fabric are cleared.
Arguments:
Name | Type | Description |
regionName | string | Region Name. Optional argument. |
Example:
| Code Block |
|---|
project = createProject()
project.addRAMLocation('module0|RAM', 'CGB[3x2]')
project.clearFabricPreplacedConstraints()
project.addRAMLocation('module0|RAM', 'CGB[4x2]') |
clearPLLs()
clearPLLs() method remove specification and location for PLLs previously added in the project.
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