...
Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation |
addBank |
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| X |
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addBanks |
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| X |
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addBlackBox |
| X |
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addDSPLocation |
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| X |
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addFalsePath |
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| X | X |
addFile | X |
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addFiles | X |
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addHSSLLocation | ||||||
addIP | X |
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addMappingDirective |
| X |
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addMaxDelayPath |
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| X | X |
addMemoryInitialization |
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| X |
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addMinDelayPath |
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| X | X |
addModule |
| X |
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addMulticyclePath |
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| X | X |
addPLLLocation |
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| X |
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addPad |
| X | X |
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addPads |
| X | X |
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addParameter | X |
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addParameters | X |
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addPin |
| X | X |
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addPins |
| X | X |
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addRAMLocation |
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| X |
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addRingLocation |
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| X |
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addRingLocations |
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| X |
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addVerilogIncludeDirectories | X |
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addVerilogIncludeDirectory | X |
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addVlogDefine | X |
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addVlogDefines | X |
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addWFGLocation |
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| X |
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adjustAperture |
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| X |
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applySdcFile | X |
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clearBanks | X |
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clearPLLs | X |
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clearPads | X |
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clearPins | X |
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clearWFGs | X |
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confineModule |
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| X |
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constrainModule |
| X | X |
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constrainPath |
| X | X |
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createAnalyzer |
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| X |
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createClock |
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| X |
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createGeneratedClock |
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| X |
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createObstruction |
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| X |
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createRegion |
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| X |
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createSimulator |
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| X |
destroy | X |
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destroyObstruction | X |
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destroyRegion | X |
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developCKGs |
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| X |
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exportAsIPCore | X |
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exportRegions | X |
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exportSites | X |
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generateBitstream |
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| X |
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generateSTANetlist | X |
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getAnalyzer | X | |||||
getDirectory | X |
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getErrorCount | X | |||||
getHierInfo | X | |||||
getLowskewSignals | X |
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getProject | X | |||||
getRemarkCount | X | |||||
getTimingUnit | X |
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getTopCellName | X |
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getVariantName | X |
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getWarningCount | X | |||||
initRegister |
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| X |
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limitLowskew |
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| X |
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listAvailableLocations | X |
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load | X |
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modifyRegion |
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| X |
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place | X |
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progress | X |
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printError | X | |||||
printHierInfo | X | |||||
printRemark | X | |||||
PrintText | X | |||||
PrintWarning | X | |||||
rejectLowskew | X |
| X |
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removeFile | X |
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removeFiles | X |
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removeSoftModules | X | |||||
reportDesignComplexity | X | |||||
reportInstances | X |
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reportLowskewSignals | X |
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reportPorts | X |
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reportRegions | X |
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reportRegisters | X |
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resetTimingConstraints | X |
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route | X |
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save | X |
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setAnalysisConditions |
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| X |
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setAperture |
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| X |
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setCaseAnalysis |
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| X |
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setClockGroup |
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| X |
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setDescription | X |
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setDeviceID |
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| X |
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setDirectory | X |
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setFalsePath |
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| X |
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setFocus |
|
| X |
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setGCKCount |
|
| X |
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setInputDelay |
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| X |
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setMaxDelay |
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| X |
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setMinDelay |
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| X |
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setMulticyclePath |
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| X |
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setOption | X |
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setOptions | X |
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setOutputDelay |
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| X |
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setSite |
|
| X |
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setTopCellName | X |
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setVariantName | X |
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synthesize | X |
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translateAperture |
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| X |
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...
| Note |
|---|
Soft modules can be removed only at Synthesis 2/3 step or before. |
eportDesignComplexity(html_file)
This method reports the design complexity, clock domain by clock domain, indicating the logic depth for all paths of the design and illustrates it with a chart in HTML format:
Name | Type | Description |
html_file | string | output HTML file name. |
Example:
| Code Block |
|---|
project.reportDesignComplexity('design_complexity.html') |
The output HTML file looks like:
...
| Anchor | ||||
|---|---|---|---|---|
|
...
This method reports the lowskew signals:
Name | Type | Description |
logfile | string | path to the logfile to report (without .log extension). |
Example:
| Code Block |
|---|
project.reportLowskewSignals('lowskew_report') |
...