...
| Code Block |
|---|
p.createClock(getClockNet('clk_1'), 'clk1', 1000010)
p.createClock(getClockNet('clk_2'), 'clk2', 1200012)
p.setClockGroup(getClock('clk1'),getClock('clk2'),'asynchronous') |
...
| Code Block | ||
|---|---|---|
| ||
p.addMinDelayPath(getRegister('i_cpt_0|s_cpt_out_reg[0]'),getRegister('i_cpt_1|s_cpt_out_reg[1]'),25008.0)
p.addMaxDelayPath(getRegister('i_cpt_0|s_cpt_out_reg[0]'),getRegister('i_cpt_1|s_cpt_out_reg[1]'),23004.0)
p.addMulticyclePath(getRegister('i_cpt_0|s_cpt_out_reg[2]'),getRegister('i_cpt_1|s_cpt_out_reg[2]'),2) |
...
| Code Block |
|---|
set_min_delay -from [get_registers {i_cpt_0|s_cpt_out_reg\[0\]}] -to [get_registers {i_cpt_1|s_cpt_out_reg\[1\]}] 8000 8 set_max_delay -from [get_registers {i_cpt_0|s_cpt_out_reg\[0\]}] -to [get_registers {i_cpt_1|s_cpt_out_reg\[1\]}] 4000 4 set_multicycle_path -from [get_registers {i_cpt_0|s_cpt_out_reg\[2\]}] -to [get_registers {i_cpt_1|s_cpt_out_reg\[2\]}] 2 |
The function getRegister gives the ability to get a register instance.
...
Path between 2 registers
| Code Block |
|---|
p.addFalsePathsetFalsePath(source=getRegister('cpt_in_p_reg[0]'),getRegister('i_cpt_0|s_cpt_out_reg[1] target=getRegisters('*')) set_false_path -from [get_registers {cpt_in_p_reg[0]}] -to [get_registers i_cpt_0|s_cpt_out_reg\[0\]*] |
Path between an input and a register.
| Code Block |
|---|
p.addFalsePathsetFalsePath(source=getPort('cpt_in[0]'), target=getRegisters('cpt_in_p_reg[`[0-13]`]')) set_false_path -from [get_ports {cpt_in\[0\]}] -to [get_registers {cpt_in_p_reg\[`[0\-3]`]}] |
Path between all registers operating on 2 clock domains.
...
| Code Block |
|---|
p.createClock(getClockNet('clk_second'),'clk_second',2000020,50005,1500015) |
=> Clock with period of 50MHz with 50% duty cycle with 90° dephasing defined by a net
| Code Block |
|---|
p.createClock(getPort('clk_main'),'clk_main',1000010,0,50005) |
=> Clock with 100MHz with 50% duty cycle defined by an IO
...
=> Clock is half the reference clock and defined by a registerEnvironment:
Here after the table of compliances for this testcase.
...
Variant
...
NG-MEDIUM NG-LARGE NG-ULTRA
...
Embedded
...
Yes
...
Simulation
...
No
...
Attributes
...
same constraints with SDC format:
| Code Block |
|---|
create_clock -period 20 -waveform {5 15} -name "clk_second" [get_ports clk_second]
create_clock -period 10 -waveform {0 5} -name "clk_main" [get_ports clk_main]
create_generated_clock -name "clk_fabric" -source [get_clocks clk_main] -divide_by 2 [get_registers {i_clock_0|counter_reg[0]}] |
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock createGeneratedClock getPort getClockNet getRegisterClock |
...
No option: Required frequency is set.
GeneratedClock: Required frequencies are set.
GeneratedClockSdc: Required frequencies are set with SDC file.
NanoXmap check: After project launching, the user can check in timing log files that required frequencies are set.
...
| Code Block |
|---|
p.setInputDelay(getClock('CLK_MAIN'),'rise',10001,1000010,getPorts('cpt_in[`[0-3]`]'))
p.setOutputDelay(getClock('CLK_MAIN'),'rise',10001,1000010,getPorts('cpt_out[`[0-3]`]')) |
getPorts method use regular expression format whereas getPort method use standard format.
Here after same constraints with SDC format:
| Code Block |
|---|
set_input_delay -clock [get_clocks "CLK_MAIN"] -min 1.0 [get_ports {cpt_in[`[0-3]`]}] set_input_delay -clock [get_clocks "CLK_MAIN"] -max 10.0 [get_ports {cpt_in[`[0-3]`]}] set_output_delay -clock [get_clocks "CLK_MAIN"] -min 1.0 [get_ports {cpt_out[`[0-3]`]}] set_output_delay -clock [get_clocks "CLK_MAIN"] -max 10.0 [get_ports {cpt_out[`[0-3]`]}] |
Environment:
Here after the table of compliances for this testcase.
...
No option: No created clock and no input or output delay is set.
InputOutputDelay: Input and output delay are set in relationship with a create clock.
InputOutputDelaySdc: Input and output delay are set in relationship with a create clock with SDC file.
NanoXmap check: After project launching, the user can check in timing log files that input and output delays are taken into account in the longest paths and that the maximum frequency is reduced drastically.
...