Page Comparison

Méthod

Project

Synthesize

Place & Route

Bitstream

STA

Simulation

addBank

X

addBanks

X

addBlackBox

X

addDSPLocation

X

addFalsePath

X

X

addFile

X

addFiles

X

addHSSLLocation

addIP

X

addMappingDirective

X

addMaxDelayPath

X

X

addMemoryInitialization

X

addMinDelayPath

X

X

addModule

X

addMulticyclePath

X

X

addPLLLocation

X

addPad

X

X

addPads

X

X

addParameter

X

addParameters

X

addPin

X

X

addPins

X

X

addRAMLocation

X

addRingLocation

X

addRingLocations

X

addVerilogIncludeDirectories

X

addVerilogIncludeDirectory

X

addVlogDefine

X

addVlogDefines

X

addWFGLocation

X

adjustAperture

X

applySdcFile

X

clearBanks

X

clearPLLs

X

clearPads

X

clearPins

X

clearWFGs

X

confineModule

X

constrainModule

X

X

constrainPath

X

X

createAnalyzer

X

createClock

X

createGeneratedClock

X

createObstruction

X

createRegion

X

createSimulator

X

destroy

X

destroyObstruction

X

destroyRegion

X

developCKGs

X

exportAsIPCore

X

exportRegions

X

exportSites

X

generateBitstream

X

generateSTANetlist

X

getAnalyzer

X

getDirectory

X

getErrorCount

X

getHierInfo

X

getLowskewSignals

X

getProject

X

getRemarkCount

X

getTimingUnit

X

getTopCellName

X

getVariantName

X

getWarningCount

X

initRegister

X

limitLowskew

X

listAvailableLocations

X

load

X

modifyRegion

X

place

X

progress

X

printError

X

printHierInfo

X

printRemark

X

PrintText

X

PrintWarning

X

rejectLowskew

 X

X

removeFile

X

removeFiles

X

removeSoftModules

X

reportInstances

X

reportLowskewSignals

X

reportPorts

X

reportRegions

X

reportRegisters

X

resetTimingConstraints

X

route

X

save

X

setAnalysisConditions

X

setAperture

X

setCaseAnalysis

X

setClockGroup

X

setDescription

X

setDeviceID

X

setDirectory

X

setFalsePath

X

setFocus

X

setGCKCount

X

setInputDelay

X

setMaxDelay

X

setMinDelay

X

setMulticyclePath

X

setOption

X

setOptions

X

setOutputDelay

X

setSite

X

setTopCellName

X

setVariantName

X

synthesize

X

translateAperture

X

Name

Default

Description

'Autosave'

'Yes'

Enable automatic protect save after each flow step.

'BypassingEffort'

'Medium'

Specify the DFF load and reset spreading level into the low-skew network (can be 'Low', 'Medium' or 'High'):

Low: all Load and Resetare sent in low skew

Medium: NXmap choose an effective balance

High: all Load and Reset are routed in common parts ( high routing constraint)

'CongestionEffort'

'High'

Specify the routing resources limit per tile (can be 'Low', 'Medium' or 'High'):

•         Low : less routing constraints but may need further more tiles and CGBs

•         Medium : balanced routing constraints but may need more tiles and CGBs

•         High : all routing resources

'Dynamic'

'No'

Refresh view while algorithms are running.

'DefaultFSMEncoding'

'OneHot'

Default encoding of finite state machine (can be 'OneHot', 'OneHotSafe', 'OneHotSafeExtra' or 'Binary'):

•         OneHot: only one bit changes per state

•         OneHotSafe: detects invalid state where all bits are ‘0’ and returns to others case

•         OneHotSafeExtra: detects invalid combinations where there is more than one bit to ‘1’ at a time

'DefaultRAMMapping'

'AUTO'

Default mapping of RAM (can be 'AUTO', 'RF', 'RAM' or 'RAM_ECC').

'DefaultROMMapping'

'AUTO'

Default mapping of ROM (can be 'AUTO', 'LUT', 'RF', 'RAM' or 'RAM_ECC').

'DensityEffort'

'Low'

Specify the instance resources allowed per tile (can be 'Low', 'Medium' or 'High'):

• Low: less resources (less routing constraints but may need more tiles and CGBs)

• Medium: well suited resources

• High: more resources (more routing constraints)

'DisableAdderBasicMerge'

'No'

Disable carry optimization around adders and subtractors.

'DisableAdderTreeOptimization'

'No'

Disable adder mux reordering and adder tree balancing.

'DisableAdderTrivialRemoval'

'No'

Disable simplification of adder that could fit in 1 or 2 LUTs.

'DisableAssertionChecking'

'No'

Deactivate VHDL assertions.

'DisableDSPAluOperator'

'No'

Disable merge of ALU within inferred DSP.

'DisableDSPFullRecognition'

'No'

Disable inference of DSP.

'DisableDSPPreOperator'

'No'

Disable merge of pre-operator within inferred DSP.

'DisableDSPRegisters'

'No'

Disable merge of registers within inferred DSP.

'DisableRegisterMergeInDspForAdd'

‘No’

Disable merge of registers in DSP when used as adder

'DisableKeepPortOrdering'

'No'

Disable keep port ordering used in source files when generating HDL netlists.

'DisableLoadAndResetBypass'

'No'

Disable load and reset signal bypass on DFF.

'DisableRAMAlternateForm'

'No'

Disable recognition of registered address read port.

'DisableROMFullLutRecognition'

'No'

Disable merge of ROM recognized as LUT with logic.

'DisableRAMRegisters'

'No'

Disable merge of registers within inferred RAM.

‘ExhaustiveBitstream’

‘No’

Can be used to force generation of all configurations and contexts in bitstream (can be ‘No’, ‘Config’, ‘Context’ or ‘ConfigContext’).

'GenerateBitstreamCMIC'

'No'

Generate bitstream with CMIC.

'IgnoreRAMFlashClear'

'No'

Do not output error when recognizing a RAM with flash clear.

'ManageAsynchronousReadPort'

'No'

If 'Yes', detect asynchronous read port in memories and repair it in synchronous read port. The read port receive the reversed write clock. It can slow down the design and sometimes may cause invalid behavior.

'ManageUnconnectedOutputs'

'Error'

Undriven outputs of HDL modules are treated as 'Error', 'Ground' or 'Power'.

'ManageUnconnectedSignals'

'Error'

Undriven internal signals of HDL modules are treated as 'Error', 'Ground' or 'Power'.

'ManageUninitializedLoops'

'No'

Remove reset-less looped DFF causing extra-mapping and 'X' values in simulation (can be 'No', 'Power, ''Ground').

'MappingEffort'

'Low'

Effort for an optimized mapping (can be 'Low', 'Medium' or 'High'):

•         Low: almost no optimization

•         Medium: balanced optimizations

•         High: almost all optimizations

'MaxRegisterCount'

'2500'

Maximum number of registers handled per HDL module (not the whole design) by the synthesizer.

‘OptimizedMux’

‘Yes’

If set to 'Yes', nxmap will identify and convert every mux in the corresponding optimized 4-LUT structure.

'PartitioningEffort'

'Medium'

Define the size of the netlist subset which will be further optimized for timing goals achievement (can be 'Low', 'Medium' or 'High') :

•         Low: small part

•         Medium: medium part

• · High: huge part

'PolishingEffort'

'Medium'

It allows to regenerate locally a signal in TILE which in normal way should be provide by an others TILE in order to reduce utilization of routing resources.

• Low: deactivate

• Medium: can replicate LUT

• High: can replicate LUT and DFF

'ReadyOffWithSoftReset'

‘Yes’

Only available for NG-ULTRA variant.

It links the ready falling edge to soft reset enabling during the power off reset sequence.

‘ReplicationApproval’

‘Yes’

Allow replication in a close TILE if not possible in the current TILE.

•         No: Do not allow replication

•         Yes: Allow replication

'RoutingEffort'

'Medium'

Routing Optimization level (can be 'Low', 'Medium' or 'High'):

•         Low: no optimization

•         Medium: balanced optimizations

•         High: further optimizations but time consuming

‘Seed’

‘1789’

Seed for placing algorithm start. Depending on the seed, instances are created in a different order and placed so.

Can be used in order to generate several Place & Route with the same synthesized project.

‘SimplifyRegions’

‘Yes’

Clear module and region database:

• delete modules without instance

• delete regions without module

• merge identical regions

‘SytemOutputDriven’

'No'

Increase placing close to the ring for instances communicating with.

•         No: No priority for these instances in algorithm

•         Yes: Allow priority for these instances in alogrithm

'TimingEffort'

‘High’

Indicates level of iterations for TimingDriven algorithm.

•         Low: no iteration

•         Medium: a few iteration

•         High: more iterations

'UnusedPads'

'Floating'

State in which the pads must be set when not used. Values can be 'Floating','WeakPullUp', 'WeakPullDown'. Note that when the state is different from 'floating', all the pads are serialized in the bitstream.

Note that ‘WeakPulldown’ value is not available on NX1H35S component.

‘VariantAwareSynthesis’

‘Yes’

If set to ‘Yes’ synthesis will automatically map to equivalent resource when specific resource is depleted. For example using DSP when there are no more CY available (can be ‘Yes’ or ‘No’).

Date

Version

Revision

2020-04-02

3.0.1

Initial draft datasheet.

2020-12-18

3.0.3

Various corrections for IO names to respect ballout syntaxe now used in NXmap3 software.

2021-04-02

3.0.4

constrainPath() and constrainModule() descriptions introduced.

Updated addPad() description to clarify the applications of several options and provide trade-off examples.

2021-07-23

3.0.5

addMappingDirective() supports the mapping of ADD into LUT.

addPad() additional precisions:

• termination specified in Ohms within a range 30 to 80

• weakTermination values ‘None’ and ‘PullUp’ not allowed for NG-MEDIUM

setLogDirectory() function implemented.

addFile() supports VHDL_93, VERILOG_95, VERILOG_2K language identifiers for synthesis through NXmap3.

bestcase, worstcase and typical scenarios supported for sdf file generation.

Overview of expected expression (full path, wildcard or regular expressions or for NXpython methods) is provided in section 5.2.2 List of NXpython methods expecting expressions.