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Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation |
addBank |
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addBanks |
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addBlackBox |
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addDSPLocation |
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addFalsePath |
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addFile | X |
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addFiles | X |
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addHSSLLocation | ||||||
addIP | X |
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addMappingDirective |
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addMaxDelayPath |
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addMemoryInitialization |
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addMinDelayPath |
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addModule |
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addMulticyclePath |
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addPLLLocation |
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addPad |
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addPads |
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addParameter | X |
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addParameters | X |
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addPin |
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addPins |
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addRAMLocation |
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addRingLocation |
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addRingLocations |
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addVerilogIncludeDirectories | X |
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addVerilogIncludeDirectory | X |
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addVlogDefine | X |
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addVlogDefines | X |
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addWFGLocation |
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adjustAperture |
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applySdcFile | X |
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clearBanks | X |
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clearPLLs | X |
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clearPads | X |
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clearPins | X |
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clearWFGs | X |
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confineModule |
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constrainModule |
| X | X |
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constrainPath |
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createAnalyzer |
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createClock |
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createGeneratedClock |
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createObstruction |
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createRegion |
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createSimulator |
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destroy | X |
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destroyObstruction | X |
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destroyRegion | X |
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developCKGs |
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exportAsIPCore | X |
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exportRegions | X |
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exportSites | X |
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generateBitstream |
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generateSTANetlist | X |
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getAnalyzer | X | |||||
getDirectory | X |
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getHierInfo | X | |||||
getLowskewSignals | X |
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getProject | X | |||||
getTimingUnit | X |
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getTopCellName | X |
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getVariantName | X |
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initRegister |
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limitLowskew |
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listAvailableLocations | X |
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load | X |
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modifyRegion |
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place | X |
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progress | X |
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printError | X | |||||
printHierInfo | X | |||||
printRemark | X | |||||
PrintText | X | |||||
PrintWarning | X | |||||
rejectLowskew | X |
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removeFile | X |
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removeFiles | X |
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removeSoftModules | X | |||||
reportInstances | X |
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reportLowskewSignals | X |
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reportPorts | X |
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reportRegions | X |
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reportRegisters | X |
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resetTimingConstraints | X |
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route | X |
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save | X |
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setAnalysisConditions |
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setAperture |
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setCaseAnalysis |
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setClockGroup |
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setDescription | X |
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setDeviceID |
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setDirectory | X |
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setFalsePath |
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setFocus |
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setGCKCount |
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setInputDelay |
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setMaxDelay |
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setMinDelay |
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setMulticyclePath |
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setOption | X |
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setOptions | X |
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setOutputDelay |
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setSite |
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setTopCellName | X |
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setVariantName | X |
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synthesize | X |
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translateAperture |
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...
| Code Block | ||
|---|---|---|
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project = createProject() directory = project.getDirectory() |
getHierInfo()
This method returns the detailed hierarchy into a dictionary variable.
This method takes no argument.
Example:
| Code Block |
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project = createProject()
hierarchy = project.getHierInfo()
printText(hierarchy) |
getLowskewSignals(ignoreTop, showCandidates)
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| Code Block |
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project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12, 19, 3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3) |
...
place
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()
This method is used to run the place algorithm on a project.
...
| Code Block | ||
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project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.setOption('TimingDriven', 'Yes')
project.place() |
printHierInfo()
This method prints the detailed hierarchy of a project with the module matched and all instances per module.
This methods takes no argument.
Example:
| Code Block | ||
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project = createProject()
project.progress('Synthesize', 3)
project.printHierInfo() |
progress(step, number)
This method allows to progress through project to a given flow step.
Arguments:
Name | Type | Description |
step | string | name of the global step [Synthesis, Place or Route]. |
number | unsigned | number in the global step [(1 to 2), (1 to 5) or (1 to 3)]. Synthesize step takes (1 to 2) for number, Place step takes (1 to 5) and Route step takes (1 to 3) for number. |
Example:
| Code Block | ||
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project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.progress('Place', 3) |
...