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Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation |
addBank |
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addBanks |
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| X |
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addBlackBox |
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addDSPLocation |
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| X |
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addFalsePath |
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| X | X |
addFile | X |
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addFiles | X |
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addHSSLLocation | ||||||
addIP | X |
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addMappingDirective |
| X |
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addMaxDelayPath |
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| X | X |
addMemoryInitialization |
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| X |
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addMinDelayPath |
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| X | X |
addModule |
| X |
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addMulticyclePath |
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| X | X |
addPLLLocation |
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| X |
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addPad |
| X | X |
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addPads |
| X | X |
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addParameter | X |
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addParameters | X |
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addPin |
| X | X |
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addPins |
| X | X |
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addRAMLocation |
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| X |
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addRingLocation |
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| X |
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addRingLocations |
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| X |
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addVerilogIncludeDirectories | X |
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addVerilogIncludeDirectory | X |
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addVlogDefine | X |
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addVlogDefines | X |
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addWFGLocation |
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| X |
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adjustAperture |
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| X |
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applySdcFile | X |
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clearBanks | X |
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clearPLLs | X |
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clearPads | X |
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clearPins | X |
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clearWFGs | X |
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confineModule |
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| X |
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constrainModule |
| X | X |
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constrainPath |
| X | X |
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createAnalyzer |
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| X |
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createClock |
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| X |
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createGeneratedClock |
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| X |
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createObstruction |
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| X |
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createRegion |
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| X |
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createSimulator |
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| X |
destroy | X |
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destroyObstruction | X |
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destroyRegion | X |
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developCKGs |
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| X |
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exportAsIPCore | X |
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exportRegions | X |
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exportSites | X |
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generateBitstream |
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| X |
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generateSTANetlist | X |
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getAnalyzer | X | |||||
getDirectory | X |
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getLowskewSignals | X |
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getProject | X | |||||
getTimingUnit | X |
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getTopCellName | X |
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getVariantName | X |
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initRegister |
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| X |
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limitLowskew |
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| X |
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listAvailableLocations | X |
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load | X |
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modifyRegion |
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| X |
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place | X |
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progress | X |
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rejectLowskew |
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| X |
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removeFile | X |
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removeFiles | X |
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removeSoftModules | X | |||||
reportInstances | X |
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reportLowskewSignals | X |
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reportPorts | X |
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reportRegions | X |
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reportRegisters | X |
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resetTimingConstraints | X |
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route | X |
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save | X |
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setAnalysisConditions |
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| X |
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setAperture |
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| X |
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setCaseAnalysis |
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| X |
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setClockGroup |
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| X |
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setDescription | X |
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setDeviceID |
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| X |
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setDirectory | X |
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setFalsePath |
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| X |
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setFocus |
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| X |
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setGCKCount |
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| X |
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setInputDelay |
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| X |
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setMaxDelay |
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| X |
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setMinDelay |
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| X |
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setMulticyclePath |
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| X |
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setOption | X |
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setOptions | X |
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setOutputDelay |
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| X |
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setSite |
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| X |
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setTopCellName | X |
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setVariantName | X |
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synthesize | X |
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translateAperture |
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| X |
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| Note |
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Merging a register into the pad (DFR using instead of DFF) can be rejected for one of the following reasons:
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When a key is not in the dictionary, its value is set to default, i.e. 0 for inputDelayLine/outputDelayLine/signalSlope/outputCapacity and False for all the boolean arguments.
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| Code Block | ||||
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project.route() project.generateSTANetlist(./output_files/routed_sta_file) |
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setDeviceID
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(id)
This method is used to change the Device ID in the bitstream header before generating it.
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| Code Block | ||||
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project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
p.setDeviceID(10) #Set Device ID to 0xA
project.generateBitstream('bitstream.nxb') |
getAnalyzer()
This method returns the current analyzer associated to the project to manage STA.
This method takes no argument.
Example:
| Code Block | ||
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project = createProject()
a = project.createAnalyzer()
project.getAnalyzer().launch() |
getDirectory()
This method returns the project current directory. This directory is used as root for all relative paths passed as argument of generic functions and/or methods. The default value of the directory is the current working directory.
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