Versions Compared

Old Version 2

changes.mady.by.user Julia DAUMAL (Unlicensed)

Saved on

compared with

New Version Current

changes.mady.by.user Kévin Chopier

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.
Comment: Invert cfg_err and ref_err for low let Table12

Revision

Date

Originator

Comments

0.1

23/09/2016

Q. Croenne

Creation

1.0

18/11/2016

Q. Croenne

First campaign configuration tests results

2.0

18/01/2017

Q. Croenne

Second campaign other tests results

3.0

30/01/2018

C. Debarge

Third and fourth campaign tests results

3.1

11/07/2018

C. Debarge

Update SEL test results

3.2

20/07/2018

C. Debarge

Fix typo in SER results

3.3

23/10/2019

C. Debarge

Fix Typos

3.3.1

13/02/2020

C. Debarge

Fix Typos

...

List of Acronyms and Abbreviations

Acronym / Abbreviation

Definition

LET

Linear Energy transfer (MeV.cm2/mg)

SEL

Single Event Latchup

SET

Single Event Transient (Transient due to a particle)

SEU

Single Event Upset (Bit flip due to a particle strike)

DFF

Digital Flip Flop

CLK

Clock

TFIT

iRoC software to simulate radiation effects

ECC

Error-Correcting Code

TMR

Triple modular redundancy

DUT

Device Under Test

Definitions

Name

Definition

FABRIC

It is a two-dimensional structure organized in row and column with homogeneous width and height.

FPGA

It is an Integrated Circuit (IC) designed with configurable elements that enable the programmability of the final function in the field rather than in the semiconductor fab.

...

The ion beam cocktail below is used.

Anchor
Table3
Table3

M/Q

Ion

DUT energy [MeV]

Range [µm Si]

LET [MeV/mg/cm2]

3.25

13 C 4+

131

269.3

1.3

3.5

14 N 4+

122

170.8

1.9

3.14

22 Ne 7+

238

202.0

3.3

3.37

27 Al 8+

250

131.2

5.7

3.33

40 Ar 12+

379

120.5

10.0

3.31

53 Ni 18+

513

107.6

16.0

3.218

58 Ni 18+

582

100.5

20.4

3.35

84 Kr 25+

769

94.2

32.4

3.54

124 Xe 35+

995

73.1

62.5

...

The table below give the configurable cell under test, the occurrence in the fabric and the number of configuration of each one:

Anchor
Table4
Table4

cell name

devices/fabric

number of configuration bit 

config

49 792

1

cross_data_cell2

338 688

1

cross_data_cell_even4

1 392 384

1

cross_data_cell_odd4

1 376 256

1

cross_data_select2

112 896

2

cross_data_select4

403 200

4

cross_sys_cell2/cross_sys_cell_empty2

129 408

1

cross_sys_select2

13 464

2

mem_config

986 048

1

fabric

6 138 096

...

The occurrence of each cell in the fabric is provide by the table below.

Anchor
Table5
Table5

cell name

devices/fabric

lowskew_horizontal_buffer

168

lowskew_horizontal_repeater

432

lowskew_local_buffer

2 712

lowskew_local_repeater

1 152

lowskew_vertical_buffer

1 512

mtx_clock

8 480

dff_latch

32 256

...

  • Tow static clock staying at 0 and 1 are provided at the input of the fabric clock tree. The left and right side are driven with these 0 and 1 static clock.

  • Each Section are programmed as in the table below where a LUT of the first table is connected with the DFF at the same position in the second table

Anchor
Table6
Table6

SECTION ADDER/EXTRA LUT/REGFILE

 

CELL

Config/Context

Group

LUT config/output

1

1

1

1

1

1

1

1

0

LUT config/output

1

1

1

1

1

1

1

1

1

LUT config/output

0

0

0

0

0

0

0

0

2

LUT config/output

0

0

0

0

0

0

0

0

3

DFF context

1

1

1

1

1

1

1

1

0

DFF context

0

0

0

0

0

0

0

0

1

DFF context

1

1

1

1

1

1

1

1

2

DFF context

0

0

0

0

0

0

0

0

3

...

Finally, the output that is the data memorized in the latch is set by writing the context of the dff_cell. Its reading is done by a context reading of the dff_cell, so that AuxOut values can be arbitrarily chosen.

Anchor
Table7
Table7

WL

DFF configuration/input condition for radiative test

2

Len0

1

Len1

1

Ren0

1

Ren1

1

1

Len2

1

AuxIn

0

Ren2

1

Sync

1

0

Cen

0

PosEdge

1

Seq

1

AuxOut

0

BL:

0

 

1

 

2

 

3

 

A bit flip on red config change the clock and input condition, thus the DFF should be ignored in statistic

A bit flip on green config doesn't change the condition if the green input are set as below

RSTI

0

SYS0/1

0

SYS2:5=RSA output

0

DFF configuration/input condition for radiative test

...

For tilted incidence when comparing the cross-section for rotation angle phi=0° and 90°, the worst case at chip level is for 0°.

Anchor
Table8
Table8

DUT

Limit

(cm2/bit)

Onset

(MeV-cm2/mg)

Width

-

S

-

DUT6

5,185E-09

2,801

37,833

2,972

DUT7

5,205E-09

0,851

35,460

5,575

Weibull Fit Parameters for configuration SEU cross-section

Anchor
Table9
Table9

DUT

Ion

LET

Range

Tilt

Effective LET

Effective Range

Fluence

SEU

SEU Cross section

min σ

max σ

chip orientation phi

 

 

MeV/mg/cm2

µm

°

MeV/mg/cm2

µm

p/cm2

 

cm2/bit

cm2/bit

cm2/bit

°

6

Ne7+

3,3

202

 

3,3

202

1,00E+07

2

3E-14

4E-15

1E-13

 

6

Ar12+

10

120,5

 

10,0

121

3,85E+06

193

8E-12

7E-12

9E-12

 

6

Ni18+

20,4

100,5

 

20,4

101

5,53E+06

20133

6E-10

6E-10

6E-10

 

6

Kr25+

32,4

94,2

 

32,4

94

9,34E+05

10360

2E-09

2E-09

2E-09

 

6

Xe35+

62,5

73,1

 

62,5

73

4,10E+05

13036

5E-09

5E-09

5E-09

 

6

Ne7+

3,3

202

60

6,6

101

5,54E+06

6

2E-13

6E-14

4E-13

90

6

Ni18+

20,4

100,5

51

32,4

63

5,27E+05

6910

2E-09

2E-09

2E-09

90

6

Kr25+

32,4

94,2

45

45,8

67

5,23E+05

11609

4E-09

3E-09

4E-09

90

6

Xe35+

62,5

73,1

49

95,3

48

1,58E+05

10623

1E-08

1E-08

1E-08

90

6

Ne7+

3,3

202

60

6,6

101

1,24E+07

928

1E-11

1E-11

1E-11

0

6

Ar12+

10

120,5

60

20,0

60

5,98E+05

5880

2E-09

2E-09

2E-09

0

6

Ni18+

20,4

100,5

51

32,4

63

3,70E+05

6869

3E-09

3E-09

3E-09

0

6

Kr25+

32,4

94,2

45

45,8

67

2,77E+05

8396

5E-09

5E-09

5E-09

0

7

Al8+

5,7

131,2

 

5,7

131

3,91E+06

1

4E-14

1E-15

2E-13

 

7

Cr16+

16

107,6

 

16,0

108

1,06E+06

2003

3E-10

3E-10

3E-10

 

7

Kr25+

32,4

94,2

 

32,4

94

1,01E+06

11688

2E-09

2E-09

2E-09

 

7

Xe35+

62,5

73,1

 

62,5

73

1,95E+05

6223

5E-09

5E-09

5E-09

 

7

Al8+

5,7

131,2

60

11,4

66

1,14E+06

1784

3E-10

2E-10

3E-10

0

7

Kr25+

32,4

94,2

45

45,8

67

4,49E+05

13364

5E-09

5E-09

5E-09

0

7

Xe35+

62,5

73,1

49

95,3

48

1,17E+05

11251

2E-08

1E-08

2E-08

0

 occurrence

 

 

 

 

 

 

 

 

6138096

 

 

 

...

Anchor
Figure13
Figure13

...

Anchor
Table10
Table10

DUT

Ion

LET

Range

Tilt

Effective LET

Effective Range

Fluence

SEU

SEU Cross section

min σ

max σ

chip orientation phi

 

 

MeV/mg/cm2

µm

°

MeV/mg/cm2

µm

p/cm2

 

cm2/bit

cm2/bit

cm2/bit

°

6+7

Ne7+

3,3

202,0

 

3,3

202,0

1,00E+07

2

3,3E-14

3,9E-15

1,2E-13

 

6+7

Al8+

5,7

131,2

 

5,7

131,2

3,91E+06

1

4,2E-14

1,0E-15

2,3E-13

 

6+7

Ar12+

10,0

120,5

 

10,0

120,5

3,85E+06

193

8,2E-12

7,0E-12

9,5E-12

 

6+7

Cr16+

16,0

107,6

 

16,0

107,6

1,06E+06

2003

3,1E-10

2,9E-10

3,3E-10

 

6+7

Ni18+

20,4

100,5

 

20,4

100,5

5,53E+06

20133

5,9E-10

5,6E-10

6,2E-10

 

6+7

Kr25+

32,4

94,2

 

32,4

94,2

1,95E+06

22048

1,8E-09

1,7E-09

1,9E-09

 

6+7

Xe35+

62,5

73,1

 

62,5

73,1

6,05E+05

19259

5,2E-09

4,9E-09

5,5E-09

 

6+7

Ne7+

3,3

202,0

60

6,6

101,0

5,54E+06

6

1,8E-13

6,4E-14

3,8E-13

90

6+7

Ni18+

20,4

100,5

51

32,4

63,2

5,27E+05

6910

2,1E-09

2,0E-09

2,3E-09

90

6+7

Kr25+

32,4

94,2

45

45,8

66,6

5,23E+05

11609

3,6E-09

3,4E-09

3,8E-09

90

6+7

Xe35+

62,5

73,1

49

95,3

48,0

1,58E+05

10623

1,1E-08

1,0E-08

1,2E-08

90

6+7

Ne7+

3,3

202,0

60

6,6

101,0

1,24E+07

928

1,2E-11

1,1E-11

1,3E-11

0

6+7

Al8+

5,7

131,2

60

11,4

65,6

1,14E+06

1784

2,5E-10

2,4E-10

2,7E-10

0

6+7

Ar12+

10,0

120,5

60

20,0

60,3

5,98E+05

5880

1,6E-09

1,5E-09

1,7E-09

0

6+7

Ni18+

20,4

100,5

51

32,4

63,2

3,70E+05

6869

3,0E-09

2,9E-09

3,2E-09

0

6+7

Kr25+

32,4

94,2

45

45,8

66,6

7,26E+05

21760

4,9E-09

4,6E-09

5,1E-09

0

6+7

Xe35+

62,5

73,1

49

95,3

48,0

1,17E+05

11251

1,6E-08

1,5E-08

1,7E-08

0

 occurrence

 

 

 

 

 

 

 

6138096

 

 

 

 

NG_medium Configuration SEU cross-section(LET)

Anchor
Table11
Table11

DUT

Limit

(cm2/bit)

Onset

(MeV/cm2/mg)

Width

-

S

-

DUT6+7

5,1852E-09

0,11214

36,4286

4,44737

...

Anchor
Figure16
Figure16

...

Anchor
Table12
Table12

let

flux

Fluence_cfg

Fluence_ref

cfg_err

ref_

eff

err

cfg_double

MBU

ref_double

Fluence

_double_cfg

double_cfg_sigm

_chip_plan

crosss_section majorant

of 2 config SEU accumulation

in the same signature

62,5

200

1,26E+04

1,21E+04

416

0

6

8

0

1,58E+04

6,2E-11

1,2E-12

62,5

100

7,35E+03

7,50E+03

228

7

8

8

0

1,02E+04

1,3E-10

5,3E-13

62,5

20

1,18E+04

1,18E+04

388

24

5

5

0

1,22E+04

6,7E-11

1,2E-13

32,4

2000

3,20E+05

3,23E+05

3333

213

4

1

0

3,73E+05

1,7E-12

1,2E-12

32,4

50

3,54E+04

3,54E+04

393

2

0

0

0

3,54E+04

4,6E-12

3,4E-14

20,4

5000

1,40E+06

1,41E+06

4852

933

1

1

0

1,44E+06

1,1E-13

3,3E-13

20,4

100

4,41E+04

4,41E+04

131

8

0

0

0

4,41E+04

3,7E-12

4,8E-15

16

5000

1,95E+06

1,95E+06

3405

875

0

0

0

1,95E+06

8,4E-14

8,4E-14

10

5000

2,22E+06

2,22E+06

1027

82

1027

0

0

0

2,22E+06

7,3E-14

3,7E-17

10

1000

6,56E+05

6,56E+05

285

23

285

0

0

0

6,56E+05

2,5E-13

6,7E-18

10

200

2,09E+04

2,09E+04

0

0

0

0

0

2,09E+04

7,8E-12

2,5E-18

5,7

5000

3,66E+06

3,66E+06

792

3

792

0

0

0

3,66E+06

4,5E-14

1,8E-20

occurrence

 

 

 

 

 

 

 

 

6138096

6138096

SEU config cross-section(LET) with CMIC

...

The cross-section of single corrected error is plotted on the curve below. The EDAC is always able to correct the single error when the data is read. So, the error cross-section with EDAC is lowered at the level of the double error cross section on the curve below. DPRAM cross-section is two orders of magnitude lower than those of the config memory and the bit occurrence of 2 752 512 is lower than those of configuration bit, meaning that the DPRAM contribution to chip SER is negligible.

Anchor
Table13
Table13

Let

flux

Fluence

single

double

single_sigm

_chip_plan

single_delt

_sigma_min

single_delt

_sigma_max

double_sigma

_chip_plan

double_delta

_sigma_min

double_delta

_sigma_max

62,5

1000

2,09E+05

39167

2

6,8E-08

3,5E-09

3,5E-09

1,9E-12

1,9E-12

8,8E-12

62,5

200

5,71E+04

10949

1

7,0E-08

3,7E-09

3,7E-09

6,4E-12

6,2E-12

2,9E-11

62,5

100

1,35E+04

2497

0

6,7E-08

4,3E-09

4,3E-09

3,5E-12

3,1E-12

9,1E-12

32,4

500

1,88E+05

27232

1

5,2E-08

2,7E-09

2,7E-09

9,9E-14

9,6E-14

2,7E-13

20,4

2500

3,18E+05

36441

0

4,2E-08

2,1E-09

2,1E-09

2,7E-11

2,6E-11

7,3E-11

20,4

500

3,20E+05

37049

0

4,2E-08

2,1E-09

2,1E-09

1,8E-13

1,8E-13

4,9E-13

16

5000

2,74E+05

20481

0

2,7E-08

1,4E-09

1,4E-09

1,3E-12

1,3E-12

3,6E-12

10

5000

1,98E+06

134865

0

2,5E-08

1,2E-09

1,2E-09

1,1E-12

1,1E-12

3,1E-12

5,7

5000

3,68E+06

131960

0

1,3E-08

6,6E-10

6,6E-10

1,1E-12

1,1E-12

3,1E-12

occurrence

 

 

 

 

2752512

 

 

2752512

 

 

SEU DPRAM cross-section(LET)

...

As show the data and the curve below the DFF cross-section is below the cross-section of the configuration memory. The SET number is considered to be the output number of a matrix system to which propagate a clock a SET that make flip more than two driven DFF. The SET cross section per system matrix is bigger than the one of configuration memory but the occurrence of mtx_sys in the test design is 1008. So the cross-section is calculated in cm² per config memory, the cross-section is negligible compared to the config cross-section, meaning that the contribution to chip SER is negligible compared to the one of config.

Anchor
Table14
Table14

let

Flux

fluence_seu

seu

set

seu_sigma_chip_plan

fluence_set

set_sigma_chip_plan

62,5

2000

4,35E+06

42

429

3,0E-10

5,4E+06

7,8E-08

32,4

2000

4,93E+06

0

1

6,3E-12

4,9E+06

2,0E-10

20,4

5000

8,32E+06

0

0

3,7E-12

8,3E+06

1,2E-10

16

5000

7,35E+06

0

0

4,2E-12

7,4E+06

1,3E-10

10

5000

6,76E+06

0

0

4,6E-12

6,8E+06

1,5E-10

5,7

5000

1,20E+07

0

0

2,6E-12

1,2E+07

8,2E-11

occurrence

 

 

 

 

32256

 

1008

...

At a LET of 62.5 MeV.cm2/mg, the static error cross section deduced from static dff is correlated with the toggle dff error cross section. Thus at 62.5 MeV.cm2/mg the toggle dff error are dominated by clock SET.

Anchor
Table15
Table15

let

flux

fluence

dff_errors

all_errors

sigma_chip_plan

delta_sigma_min

delta_sigma_max

62,5

2000

1 076 442

2228

2228

6,4E-08

4,2E-09

4,2E-09

32,4

2000

952 542

460

460

1,5E-08

1,5E-09

1,6E-09

20,4

5000

2 195 681

383

383

5,4E-09

5,9E-10

6,3E-10

16

5000

2 093 467

199

199

2,9E-09

4,2E-10

4,6E-10

10

5000

2 234 373

24

24

3,3E-10

1,2E-10

1,6E-10

5,7

5000

3 606 304

17

17

1,5E-10

6,1E-11

8,8E-11

...

SEFI were recorded, a SEFI in the FPGA control part mean that the reading or writing of the configuration/context is not possible, while the application status is unknown. The SEFI cross-section contribution to chip cross-section is negligible compared to the one of config.

Anchor
Table16
Table16

let

flux

fluence

periods

sefi

sefi_sigma

_chip_plan

sefi_delta

_sigma_min

sefi_delta

_sigma_max

sefi_sigma

_chip_plan per config

sefi_delta

_sigma_min

sefi_delta

_sigma_max

62,5

2000

3,56E+06

93

13

3,7E-06

1,7E-06

2,6E-06

5,9E-13

2,8E-13

4,2E-13

62,5

1000

2,38E+05

14

1

4,2E-06

4,1E-06

1,9E-05

6,9E-13

6,7E-13

3,1E-12

62,5

200

7,96E+04

24

2

2,5E-05

2,2E-05

6,6E-05

4,1E-12

3,6E-12

1,1E-11

62,5

100

2,54E+04

15

0

3,9E-05

3,8E-05

1,1E-04

6,4E-12

6,3E-12

1,7E-11

62,5

20

1,22E+04

36

0

8,2E-05

8,0E-05

2,2E-04

1,3E-11

1,3E-11

3,6E-11

32,4

2000

4,26E+06

61

21

4,9E-06

1,9E-06

2,6E-06

8,0E-13

3,1E-13

4,3E-13

32,4

500

2,59E+05

17

2

7,7E-06

6,8E-06

2,0E-05

1,3E-12

1,1E-12

3,3E-12

32,4

50

3,54E+04

20

0

2,8E-05

2,8E-05

7,6E-05

4,6E-12

4,5E-12

1,2E-11

20,4

5000

7,04E+06

52

5

7,1E-07

4,8E-07

9,5E-07

1,2E-13

7,8E-14

1,5E-13

20,4

2500

3,31E+05

5

0

3,0E-06

3,0E-06

8,1E-06

4,9E-13

4,8E-13

1,3E-12

20,4

500

3,38E+05

20

1

3,0E-06

2,9E-06

1,4E-05

4,8E-13

4,7E-13

2,2E-12

20,4

100

4,41E+04

17

0

2,3E-05

2,2E-05

6,1E-05

3,7E-12

3,6E-12

9,9E-12

16

5000

1,07E+07

66

16

1,5E-06

6,5E-07

9,4E-07

2,4E-13

1,1E-13

1,5E-13

10

5000

9,11E+06

63

2

2,2E-07

1,9E-07

5,7E-07

3,6E-14

3,1E-14

9,3E-14

10

1000

6,89E+05

22

1

1,5E-06

1,4E-06

6,6E-06

2,4E-13

2,3E-13

1,1E-12

10

200

2,09E+04

3

0

4,8E-05

4,7E-05

1,3E-04

7,8E-12

7,6E-12

2,1E-11

5,7

5000

1,81E+07

117

19

1,1E-06

4,2E-07

5,9E-07

1,7E-13

6,9E-14

9,7E-14

occurrence

 

 

 

 

1

 

 

6138096

 

 

...

The table and graphic below give the measured cross-section for the two chips under test and the Weibull fittings. Since DUT #53 and DUT #52 measurements are correlating correctly, the two chips data are merged for the next curves and studies.


Anchor
Table17
Table17

DUT

Energy

MeV

Fluence

SEU

SEU Cross section

min σ

max σ

 

p/cm2

 

cm2/bit

cm2/bit

cm2/bit

53

50

1,18E+10

3

4.16E-17

8,51E-17

1,21E-16

53

100

7,92E+10

109

2,24E-16

1,83E-16

2,72E-16

53

150

6,00E+10

100

2,72E-16

2,19E-16

3,32E-16

53

230

5,00E+10

153

4,99E-16

4,19E-16

5,88E-16

52

30

3,80E+09

1

4,29E-17

1,03E-18

2,39E-16

52

50

1,77E+10

7

6,43E-17

2,57E-17

1,33E-16

52

100

4,00E+10

58

2,36E-16

1,78E-16

3,06E-16

52

150

5,85E+10

108

3,01E-16

2,45E-16

3,65E-16

52

230

6,00E+10

184

5,00E-16

4,26E-16

5,81E-16

 occurrence

 

 

6138096

 

 

Configuration SEU cross-section(energy) of DUT #53 and DUT #52

Anchor
Table18
Table18

DUT

Limit

(cm2/bit)

Onset

(MeV)

Width

-

S

-

DUT53

4.82959e-016

49.99900

12.87336

0.37122

DUT52

4.84232e-016

29.99900

28.16281

0.47816

...

Anchor
Figure21
Figure21

...

Anchor
Table19
Table19

DUT

Energy

MeV

Fluence

SEU

SEU Cross section

min σ

max σ

 

p/cm2

 

cm2/bit

cm2/bit

cm2/bit

52+53

30

3,80E+09

1

4,29E-17

1,03E-18

2,39E-16

52+53

50

1,77E+10

7

6,43E-17

2,57E-17

1,33E-16

52+53

100

4,00E+10

58

2,36E-16

1,78E-16

3,06E-16

52+53

150

5,85E+10

108

3,01E-16

2,45E-16

3,65E-16

52+53

230

6,00E+10

184

5,00E-16

4,26E-16

5,81E-16

 occurrence

 

 

6138096

 

 

Configuration SEU cross-section(energy) for merged DUT #53 + DUT #52

Anchor
Table20
Table20

DUT

Limit

(cm2/bit)

Onset

(MeV)

Width

-

S

-

DUT53+52

4,85e-016

29,99900

29,68

502E-3

...

CMIC stops when 2 errors occur in the same signature. No double error in a same signature is observed in the reference memory (ST_SPREG_144x27m4). The configuration double error in a same signature cross section is calculated by dividing the double error number by config number and fluence.

Anchor
Table21
Table21

DUT#

Energy MeV

Fluence cfg

cfg_err

cfg_sigma

_chip_plan

cfg_delta sigma min

cfg_delta sigma max

53

230

1,254E+11

484

6,29E-16

6,32E-17

6,65E-17

52

230

8,7733E+10

286

5,31E-16

6,54E-17

7,05E-17

occurrence

 

 6138096

 

 

SEU config cross-section(energy) with CMIC for single error

Anchor
Table22
Table22

DUT#

Energy MeV

Fluence double cfg

double cfg_err

double cfg_sigma

_chip_plan

double cfg_delta sigma min

double cfg_delta sigma max

53

230

1,3E+11

1

1,25E-18

1,22E-18

5,73E-18

52

230

9,66E+10

2

3,37E-18

2,97E-18

8.81E-18

occurrence

 

 6138096

 

 

...

The cross-section of single corrected error is plotted on the curve below. The EDAC is always able to correct single errors when the data is read. So, For this test, the clock frequency used by the design is 10MHz.

Anchor
Table23
Table23

DUT #

Energy

Fluence

single errors

sigma_chip_plan

delta_sigma_min

delta_sigma_max

53

230

1,00E+10

2448

8,89E-14

5,65E-15

5,72E-15

53

100

1,21E+10

2287

6,87E-14

4,42E-15

4,48E-15

53

50

1,05E+10

1977

6,83E-14

4,53E-15

4,60E-15

53

30

7,00E+09

1317

6,84E-14

4,99E-15

5,11E-15

52

230

1,08E+11

22874

7,69E-14

3,97E-15

3,97E-15

52

100

3,19E+10

5547

6,32E-14

3,57E-15

3,58E-15

52

50

2,12E+10

3586

6,15E-14

3,67E-15

3,69E-15

52

30

1,61E+10

2844

6,43E-14

3,98E-15

4,02E-15

occurrence

 

 

2752512

 

 

single SEU DPRAM cross-section (energy)


Anchor
Table24
Table24

DUT #

Energy

Fluence

double errors

sigma_chip_plan

delta_sigma_min

delta_sigma_max

53

230

1,00E+10

0

3,63E-17

3,55E-17

9,77E-17

53

100

1,21E+10

0

3,00E-17

2,93E-17

8,07E-17

53

50

1,05E+10

0

3,46E-17

3,37E-17

9,29E-17

53

30

7,00E+09

0

5,19E-17

5,07E-17

1,40E-16

52

230

1,08E+11

0

3,36E-18

3,28E-18

9,03E-18

52

100

3,19E+10

1

1,14E-17

1,11E-17

5,21E-17

52

50

2,12E+10

0

1,72E-17

1,67E-17

4,61E-17

52

30

1,61E+10

0

2,26E-17

2,21E-17

6,08E-17

occurrence

 

 

2752512

 

 

...

The SET number is considered to be the output number of a matrix system to which propagate a clock a SET that make flip more than two driven DFF. No SET where detected during the test.

Anchor
Table25
Table25

DUT#

Energy (MeV)

seu

fluence_seu

seu_sigma_chip_plan

seu delta sigma min

seu delta sigma max

53

230

1

9,00E+10

3,44E-16

3,36E-16

1,57E-15

52

230

2

9,00E+10

6,89E-16

6,06E-16

1,80E-15

occurrence

 

 

32256

...

The curve below shows the dff context error cross section per dff and per config. The cross section per config is below the configuration cross section, meaning that for toggle dff application the chip SER contribution is below than the one of configuration memory.

Anchor
Table26
Table26

DUT #

fabric frequency (MHz)

Energy (MeV)

dff errors

fluence

sigma_chip_plan

delta_sigma_min

delta_sigma_max

53

60

100

1

2,01E+10

1,54E-15

1,51E-15

7,06E-15

53

60

150

13

3,93E+10

1,03E-14

4,82E-15

7,30E-15

53

60

230

17

5,51E+10

9,57E-15

4,02E-15

5,77E-15

52

60

100

7

3,26E+10

6,66E-15

3,99E-15

7,07E-15

52

60

150

13

5,32E+10

7,58E-15

3,56E-15

5,39E-15

52

60

230

32

9,03E+10

1,10E-14

3,51E-15

4,56E-15

...

The curve below shows the dff context error cross section per dff relative to the fabric clock frequency, we can see little to no effect for the tested frequencies (10MHz, 35MHz, 60MHz). The test vehicle was not designed to support higher fabric frequencies.

Anchor
Table27
Table27

DUT #

fabric frequency (MHz)

Energy (MeV)

fluence

dff_errors

sigma_chip_plan

delta_sigma_min

delta_sigma_max

53

10

230

4,27E+10

13

9,44E-15

4,44E-15

6,72E-15

53

35

230

5,67E+10

14

7,65E-15

3,49E-15

5,20E-15

53

60

230

5,51E+10

17

9,57E-15

4,02E-15

5,77E-15

52

10

230

9,00E+10

19

6,54E-15

2,62E-15

3,69E-15

52

60

230

9,03E+10

32

1,10E-14

3,51E-15

4,56E-15

...

SEFI were recorded. A SEFI in the FPGA control part mean that the reading or writing of the configuration/context is not possible, while the application status is unknown. The SEFI cross-section contribution to chip cross-section is negligible compared to the one of config.

Anchor
Table28
Table28

DUT #

energy

Fluence

sefi

sefi_sigma

_chip plan

sefi_delta

_sigma min

sefi_delta

_sigma_max

sefi_sigma

_chip_plan

per config

sefi_delta

_sigma_min

per config

sefi_delta

_sigma_max

per config

53

230

5,25E+11

1

1,90E-12

1,86E-12

8,71E-12

3,10E-19

3,03E-19

1,42E-18

53

150

9,93E+10

1

1,01E-11

9,83E-12

4,60E-11

1,64E-18

1,60E-18

7,50E-18

53

100

1,29E+11

1

7,75E-12

7,57E-12

3,54E-11

1,26E-18

1,23E-18

5,77E-18

53

50

2,81E+10

1

3,56E-11

3,47E-11

1,63E-10

5,80E-18

5,66E-18

2,65E-17

53

30

1,24E+10

0

8,06E-11

7,87E-11

2,17E-10

1,31E-17

1,28E-17

3,53E-17

52

230

6,04E+11

3

1,10E-10

3,95E-12

9,55E-12

8,09E-19

6,44E-19

1,56E-18

52

150

1,42E+11

1

2,80E-11

6,89E-12

3,23E-11

1,15E-18

1,12E-18

5,26E-18

52

100

2,81E+11

1

3,56E-12

3,47E-12

1,63E-11

5,80E-19

5,66E-19

2,65E-18

52

50

3,57E+10

0

7,06E-12

2,73E-11

7,53E-11

4,56E-18

4,45E-18

1,23E-17

52

30

9,07E+09

0

4,97E-12

1,08E-10

2,96E-10

1,80E-17

1,75E-17

4,83E-17

occurrence

 

 

1

 

 

6138096

 

 

...

The SER for the four given mission profiles are given in the table below:

Anchor
Table31
Table31

Mission profile

SER (bit/day)

SER (chip/day)

GEO

2,05E-10

1,26E-3

MEO

1,30E-09

7,98E-3

LEO1 Pol

2,57E-09

1,58E-2

LEO2 ISS

3,06E-10

1,88E-3

...