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Each byte (or word) is written on the rising edge of CLK, while CS_N and WE_N are activated (low level) simultaneously. Dummy cycles can be inserted – if required by the master by de-asserting both CS_N and WE_N during one or more cycles between any two consecutive bytes. The next figure illustrates an example of timing diagram.
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Hereafter the setup and hold times for Slave parallel NG-MEDIUM configuration interface:
PAD | setup time (ps) | hold time (ps) |
RST_N | 1354 | 106 |
CS_N | 1879 | 19 |
WE_N | 785 | 247 |
D0 | -454 | 481 |
D1 | -146 | 445 |
D2 | -222 | 395 |
D3 | -19 | 421 |
D4 | 836 | 181 |
D5 | 16 | 451 |
D6 | -17 | 435 |
D6 | -96 | 495 |
D8 | 244 | 471 |
D9 | 268 | 353 |
D10 | 1188 | 212 |
D11 | 739 | 341 |
D12 | 1327 | 361 |
D13 | 2138 | 247 |
D14 | 819 | 331 |
D15 | 935 | 341 |
PAD | CKtoQ_min | CKtoQ_max |
READY | 3125 | 7156 |
ERROR | 2926 | 6219 |
DATA_OE | 3526 | 8993 |
Internal interface between fabric and BSM
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