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NX1H35AS chips are always accessible through JTAG, and also support several configuration modes. At power-up, MODE[3:0] pins state define the configuration mode. RST_N is a dedicated input pin that allows to reset the configuration engine, and launches the configuration process after RST_N is released. (It can’t be used to reset the FPGA user’s logic).
When MODE[3]='0', internal 50 MHz is used as Bitstream manager clock. Otherwise, user must provide an external clock.
MODE[3:0] | Configuration mode |
|---|---|
0000 0x0 | RESERVEDMaster Serial |
0001 0x1 | RESERVEDJtag Only |
0010 0x2 | Master Serial SPI |
0011 0x3 | Master Serial SPI with Vcc control |
0100 0x4 | Slave SpaceWire |
0101 0x5 | RESERVED |
0110 0x6 | Slave Parallel 8 |
0111 0x7 | Slave Parallel 16 |
1000 0x8 | Master Serial |
1001 0x9 | RESERVED |
1010 0xA | Master Serial SPI |
1011 0xB | Master Serial SPI with Vcc control |
1100 0xC | Slave SpaceWire |
1101 0xD | RESERVED |
1110 0xE | Slave Parallel 8 |
1111 0xF | Test Mode |
| Anchor | ||||
|---|---|---|---|---|
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