Page Comparison

GLOBAL

MODE(3 :0)

I

Input pins sampled at power-up. MODE(3:0). They define the configuration mode to be used for NG-MEDIUM configuration. MODE(3:0) cannot be changed when RST_N = ‘1’

CLK

I

Required only for slave parallel 8/16 configuration (20 or 50 MHz). For other

configuration modes, must be tied to 3.3V via 10KOhms pullup resistor

RST_N

I

Mandatory input. When low, it resets the internal configuration engine. RST_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_N goes high, the configuration starts after up to 3

additional microseconds.

READY

O

Goes high when the configuration is complete (the FPGA enters in user’s mode)

ERROR

O

Generates a high level pulse (~20 ns or one CLK cycle) each time an error is

encountered during the configuration.

Slave Parallel 8

CS_N

I

Active low Chip_Select input. Used in Slave Parallel 8 mode. The master can

write or read to/from the configuration engine when CS_N is low during a CLK rising edge.

WE_N

I

Active low Write_Enable input. Used in Slave Parallel 8 mode. The master can

write to the configuration engine when both CS_N and WE_N are low during a CLK rising edge.

DATA_OE

O

This pin is reserved. Must be left unconnected

D(7 :0)

I/O

8-bit data bus used in Slave Parallel 8 mode to write the bitstream and/or read

internal NG-MEDIUM internal state values