...
| Anchor | ||||
|---|---|---|---|---|
|
Frequency clock configuration for Master Serial SPI Mode / Master Serial SPI Mode with VCC control
The frequency of SPI clock is defined by the field spi_clk_ratio, inside the SPI_CTRL register, handled by the Bitstream Manager. spi_clk_ratio defines the divider applied to the SPI clock, the default value is 17 which implies the following default SPI frequency : spi_clk/spi_clk_ratio = 50MHz / 17 = 3MHz.
The default SPI clock value in the generated bitstream aimed to be programmed in the Flash SPI memory can be modified using the NXmap3 method initRegister(command, value).
As an example, the user would like to modify the default 3MHz frequency of SPI clock to increase it to 13MHz. To do so, the default value 0x01f4003f of SPI_CTRL register must be overridden with the corresponding change for spi_clk_ratio field : spi_clk_ratio = 2 implies 50MHz / (2+2) = 13MHz (see details in the spi_clk_ratio values of SPI_CTRL). The SPI_CTRL register value obtained is 0x01f40032. In order to program this value into the bitstream, the user must declare the following command during flow execution in NXmap3:
project.initRegister('SPI_CTRL', '0x01f40032')
project.generateBitstream('bitstream.nxb')
Then the SPI Flash memory is programmed with the bitstream. After this, the FPGA configured in master SPI mode will load the bitstream from the memory and the SPI clock frequency will change from 3MHz to 13MHz once the corresponding instruction in the bitstream will be read.
Slave SpaceWire configuration details:
...