NG-ULTRA
The NG-ULTRA NX2H540TSC is the world’s first Radiation Hardened By Design (RHBD) SoC FPGA in 28nm with quadcore ARM R52 running at 600MHz each, based on 28nm FD-SOI Technology Platform from STMicroelectronics. It has a logic capacity of 550k LUTs. The hardening techniques used in the NG-ULTRA alongside the FD-SOI technology offers very strong hardening performance.
As shown in Figure above, NG-ULTRA NX2H540TSC contains two parts: programmable logic matrix and Microprocessor subsystem. First part is quite similar with previous device. It is composed of a central fabric embedding the programmable logic, RAM and DSP blocks. The fabric takes benefit from the high-speed connectivity such as High-Speed Serial Links (HSSLs) and DDR2/3 interfaces. It is covered with a grid of high-level functional blocks interleaved with interconnect structures providing routing resources to realize the connections within the fabric and to the peripheral I/Os. The programmable logic resources are arranged in a hierarchical structure called a TILE with a specific local interconnect network. I/Os are arranged into multiple banks. Each bank has its own I/O buffer supply voltage. Second part is the microprocessor subsystem which is based on a complete System on Chip.
Documentation
As a radiation hardened FPGA, the NG-ULTRA NX2H540TSC will go through a qualification process for flight applications. The datasheet of the NG-ULTRA is divided in two parts:
FAMILY datasheet applies for RHBD unqualified component V2:
FAMILY datasheet applies for RHBD unqualified component V2B:
NG-ULTRA PS User Manual describes in details the System on Chip, this documentation is currently under work. Under work version : NG-ULTRA PS USER MANUAL V0.3
Configuration Guide give details about different solutions to boot NG-ULTRA:
Radiation test campaigns are reported in order to confirm NG-ULTRA robustness:
Heavy Ion Radiation Test Report
To map an application into the NG-ULTRA target variant through NXmap environment, an assignment file of all IOs available associated to NG-ULTRA pads can be used:
The complete NG-ULTRA NX2H540TSC ballout is available in the following page:
Schematic symbols (Altium):
Footprint (Altium):
As the first FPGA developped by NanoXplore integrating a complex System on Chip system interacting with the programmable matrix, the NG-ULTRA NX2H540TSC component requires a boot loading sequence to start from the loading the bitstream file available through several potential interfaces (SPI, SpaceWire) and to enable specific hardware functionalities related to the SOC management. To do so, a series of application notes are provided to help users going through these peculiar steps:
Use the following one to launch a boot loading sequence with a bitstream read from a flash memory: NG-ULTRA BL1 Flash memory
NG-ULTRA incorporates a security process to load a bitstream using encryption mechanisms described in the dedicated page : NG-ULTRA bitstream loading security
Given specific configuration and context used to program resources of the FPGA matrix, the size of the bitstream generated may vary based on what is used for the application. The Bitstream Size Estimator gives an estimation on which resources will have an impact on the size of the bitstream:
Bitstream Size Estimator NG-ULTRA
NanoXplore provides characterized data through IBIS models for temperature and corner case conditions aimed for simulation works. Power consumption estimation can be computed using NXPowerEstimator for any project application given which kind and how many resources will be used to map the design:
NG-ULTRA IBIS model : ngultra_ibis.zip
NX Power estimator for NG-ULTRA : NXPowerEstimator_NGULTRA_v2_2b.xlsm
IPs compatible with NG-ULTRA
NanoXplore is willing to develop internal IPs for NG-ULTRA use and already work with third-partner providers for some IPs currently available within the NXcore tool, part of the NXmap software chain.
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