List of figures

SERDES IP Core

SERializer IP Core.

DESerializer IP Core

Introduction and overview

NanoXplore provides a user’s customizable IP Core generator for complex IO banks SERializers and DESerializers applications implementation.

The SER/DES IP Core is able to implement multi-channel SERialization, DESerialization and SER/DES applications.

The IP Core instantiates al the required number NX_SER and NX_DES of a same SER_DES group and provides DESerializers automatic adjustments (data/clock and word alignment) for high speed safe communications. It also includes a mechanism that allows to send a user’s defined training value to external receivers.

In addition, the IP Core generates automatically all internal clocks by using a Clock Generator (CKG), taking as reference the incoming word clock.

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SERDES IP Core

Note that the delay of the SERializers outputs is static, but it’s still user’s defined. I can’t be modified by the calibration process.

The IP Core can manage simultaneously SERializers  and DESerializers in a same group – while they share some common parameters, such as :

• All SER and all DES must be located in a single complex IO bank the following sets:

• All elements located in the same bank must use an electrical standard compatible with the VCCIO of the bank

• All SER and DES of a same group must share the same bit rate and word rate, and then the same serialization/deserialization factor.

The maximum total number of SER and DES elements in a same group is 30 (no differential mode and serialization/deserialization factor from 2 to 5), or 15 in differential mode or serialization/deserialization factor from 6 to 10.

In a same NG-MEDIUM design, up to 4 SER/DES groups can be implemented.

The IP Core can be also used for application requiring only SERializers or DESerializers.

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SERializer IP Core

This IP Core generates all required functions for SER and/or DES applications.

• Instantiates the number of required DES

• Instantiates the number of required SER

• Allows to define all parameters for SER and DES

• Generates all necessary clocks (using a CKG block)

• Includes automatic data/clock alignment on the DES inputs

• Includes automatic DESerializers word alignment

• User’s defined pattern generation for SERializers to external receiver (training value)

• Provides inputs and outputs for commands, handshake and status

IP Core parameters

All parameters are user’s defined. Among available parameters :

  Global parameters :

• Word_clock_freq : Frequency of the word clock (integer value in MHz)

• Data_size : serialization/deserialization factor

• NUMBER_OF_DES : number of DES in the considered group

• NUMBER_OF_SER : number of SER in the same group

• BANK_NUMBER : the number of the complex bank where the group of SER/DES must be located

DES specific parameters

Apply to all DES in the considered group. Those parameters are the same that apply to NX_IOB_I

• Des_pad_type : electrical standard of all DES in the considered group

• Des_differential

• Des_termination

• Des_termination_reference

• Des_weakTermination

• Des_turbo

• Des_inputSignalSlope

• Des_location : number of the I/O in the considered bank (array of strings like ("01P", "05N", "12P")

• Des_delay_on : must be removed from parameters list

• Des_dpath_dynamic : when '1', allows automatic calibration

• Des_inputDelayLine : default delay value for each DES (array of strings). Note that the input delay value is overridden by the optimal value during the calibration process.

• Des_trainingValue : word value to be recognized during the data/clock alignment sequence

SER specific parameters

Apply to all SER in the considered group. They are the same that apply to NX_IOB_O

• Ser_pad_type

• Ser_differential

• Ser_slewRate

• Ser_outputCapacity

• Ser_location : number of the I/O in the considered bank (array of strings like "02P", "06N", "15P")

• Ser_delay_on : should be removed from parameters list

• Ser_spath_dynamic : ????

• Ser_outputDelayLine : one static value for each SER (array of strings). Ser_outputDelayLine value is not affected by the calibration process.

• ser_trainingValue : word value to be sent during the data/clock alignment sequence on the receiver side

Basic recommendations for correct implementation:

• The bitrate at DES inputs and SER outputs must be compliant with the chosen electrical standard.

• In any case, the maximum bit rate must be  in the range 150 Mb/s to 800 Mb/s

• The word rate and then the word clock frequency must be in the range 20 MHz to 200 MHz

• All SER and DES of the same group must share the same bit rate and word rate, and will be located in the same complex bank. The CKG block (PLL + WFGs) will be located in the neighboring location :

• The word clock must be provided via a dedicated clock pin with direct access to the required CKG block :

SERDES IP Core inputs and outputs:

Clocks related inputs and outputs

• CLKIN_SERDES - input : word clock input

• SCK_OUT - output : internally generated word clock image distributed on the low skew network (clock tree) for optional usage in other portions of the design. Of course this clock is also used in the IP Core.

• DCK_OUT – output : the data/clock alignment requires an independent clock for reading and writing delay registers. This clock is generated in the same CKG block, and its frequency the word clock frequency divided by 4. It’s distributed by a clock tree. Optionally, this clock can be used in other portions of the design.

Control related inputs and outputs

• RST_OUT – output : This signal remains high while the PLL is not locked (the internally generated clocks are not working properly). RST_OUT can be used to reset external IP Core logic or to prevent activity until it comes low.

• LAUNCH_CALIB - input : After RST_OUT has been de-asserted, a high pulse of 2 to 16 word clock periods must be applied to this input in order to start the data/clock and word alignment process (this process is also called CALIBRATION).

• TRAINING_REQUEST_OUT - output : Active high. The IP Core informs that it requires an external transmitter device to send continuously a specific value – called “DES_TrainingValue” to the deserializers (receivers) being part of the IP Core. TRAINING_REQUEST_OUT goes back low after the calibration (bit & word alignment) process is complete (see CALIB_DONE output).

• TRAINING_ACK_IN - input : When high, the transmitter informs that it received the request for receiver calibration, and it’s currently sending the required training value.

• TRAINING_REQUEST_IN - input : Active high. If the IP Core is used as transmitter, it must send the expected “SER_TrainingValue” to the receiver. This is the training request signal coming from the external receiver device.

• TRAINING_ACK_OUT - output : When high, the IP Core transmitter informs that it received the calibration request from the receiver, and it’s currently sending the required “SER_trainingValue”. TRAINING_ACK_OUT must go back low if TRAINING_REQUEST_IN goes low.

• CALIB_DONE - output : Goes high when the calibration (DESerializers data/clock and word alignment) process is complete.

• CALIB_ERROR - output : Goes high if the calibration could not complete successfully.

Data related inputs and outputs

• RX(MD-1 downto 0) - input : DESerializer(s) input pad name. “MD” is the number of deserializers used in the current SER/DES group.

In the DESerializers, the data are coming at the bit rate, and are deserialized by words at the word rate. All IO related parameters values (IO location, electrical standard, differential or not, termination and other parameters) are defined by the user in the SERDES IP Core generator.

The SERDES IP Core is able to implement multi-channel deserialization. Tacking as reference the word clock (CLKIN_SERDES) it generates automatically the required clocks

The SERDES IP Core ensures data/fast clock alignment on each RX input. It also provides word alignment.

• DOUT(MD-1:0)(N-1:0) (array of outputs) : Deserialized and word aligned output to the fabric.“MD” is the number of deserializers, “N” is the deserialization factor – common to all deserializers and serializers of a same group.

The SERDES IP Core is able to implement multi-channel deserialization. It ensures data/fast clock alignment on each RX input as well as word alignment.

Each deserializer deserializes its own stream and provides a parallel DOUT word after the calibration process (bit alignment and word alignment) properly completes.

• TX(MS-1 downto 0) - output : Serializer(s) output pad name. “MS” is the number of serializers used in the current SER/DES group.

In the SERializers, the serialized data are sent to the TX pads at the bit rate (LSB first). 

All IO related parameters values (IO location, electrical standard, differential or not, slew rate and other parameters) are defined by the user in the SERDES IP Core generator.

The SERDES IP Core is able to implement multi-channel serialization and deserialization. Tacking as reference the word clock (CLKIN_SERDES) it generates automatically the required clocks.

Each SERializer can use the output delay line to delay the output data relatively to the the bit clocks. The delay is fixed for a given bitstream. It can be adjusted via the GRPX_ser_outputDelayLine parameter.

• DIN(MS-1:0)(N-1:0) - array of inputs : Inputs for the words to be serialized (coming from fabric). “MS” is the number of serializers, “N” is the serialialization factor – common to all serializers and deserializers of a same group.