NxDesignSuite 23.5 Design Flow

Owned by Kévin Chopier
21 Dec, 2023
38 min read

 

Copyright Notice

This document and all of its contents are protected by French and international laws on copyright and intellectual property. They may not be copied, duplicated, reproduced or otherwise disclosed in any form, in whole or in part, to any person or organisation without the prior express written consent of NanoXplore.

 

Introduction

The purpose of this document is to guide users of NanoXplore Impulse software through the steps involved in the design flow and to describe the options available in the NanoXplore Design Suite:

  • Impulse
    A graphical user interface providing all the options necessary to complete your entire design flow and floorplanning exploration

  • nxpython
    A wrapper around a Python executable that enables you to control Impulse software as a wrapper

    • nxpython fully supports Python syntax, structures and external modules

    • All commands for nxpython described in this document can be applied to the VHDL examples provided in the example folder

You can create new projects using either Impulse or nxpython

 

Requirements

Impulse is intended to operate on a 64 bits Linux workstation running one of the following distributions:

  • CentOS 7

  • CentOS 8

  • RedHat Enterprise Linux 7

  • RedHat Enterprise Linux 8

Impulse has also been tested on the following distributions:

  • UBUNTU 18

  • UBUNTU 20

  • DEBIAN 11

Impulse requires Python however, to prevent conflicts, we do not provide a preinstalled version of Python with Impulse. Python must therefore be installed on the user's workstation. Impulse is compatible with Python versions 3.6 and above.

 

For any other distribution or platform issues, please contact the NanoXplore support team: support@nanoxplore.com.

When a command argument appears with parentheses around the brackets, e.g. “([argument])”, this means the argument is optional

System Requirements

 

Minimum Requirements

Recommended Requirements

 

Minimum Requirements

Recommended Requirements

CPU Speed/Processor

3GHz Quad-Core

3GHz 8-Core

Memory

8GB RAM

16GB RAM

Disk Capacity/Type

2GB (HDD)

2GB (SSD)

Package Description

The Impulse archive provided contains the following directories.

Directory Name

Folder Contents

Directory Name

Folder Contents

bin 

Binary files for each supported Linux distribution

doc

Documentation files in PDF format

example

Various examples of different projects with VHDL design sources

lib64

Dynamic libraries and Python modules for each supported Linux distribution and associated Python version

share

Additional files (VHDL libraries, simulation libraries, etc.)

Installation

To install Impulse:

  1. Unpack the compressed nxdesignsuite-VERSION.tar.gz file to the installation directory of your choice
    (e.g. /opt/NanoXplore) using the following command:

    $> tar xzf nxdesignsuite-VERSION.tar.gz -C /opt/NanoXplore

  2. Set the licence by exporting the following shell variable*:

    $> export LM_licence_FILE=27000@servername

*Where servername is the hostname of the server running the licence daemon and 27000 is the port the daemon listens to.

Run Impulse

To run Impulse, use the following command:

$> /opt/NanoXplore/impulse/VERSION/bin/impulse

Run nxpython

To run nxpython, use the following command:

$> /opt/NanoXplore/impulse/VERSION/bin/nxpython

To access Python functionalities in Impulse, call the following command in nxpython:

from nxpython import *

Design Flow Overview

The entire Design Flow is performed in NanoXplore NX tools:

  • Impulse (the dedicated NX graphical user interface), or

  • nxpython (the NX Python command-line tool)

 Impulse supports VHDL and Verilog

Impulse Design Flow

  • Impulse is a graphical interface to guide you through Project creation, as well as debug and inspect the design at various stages. For more information on Impulse, please see Impulse (Graphical User Interface)

  • nxpython is a Python wrapper to control Impulse. It fully supports Python syntax, structures and external modules. You can use nxpython for the entire design flow or any specific step in the flow

  • Both Impulse and nxpython are fully compatible so that any file generated by one can be used by the other at any stage in the design flow

NanoXplore design environment does not include any simulation tools, however, you can use third-party tools to simulate or verify the design by using HDL files generated by NanoXplore Design Flow

Project Creation

Creating a new project starts “from scratch”, which involves defining a project directory, adding sources and configuring settings which can be compulsory or optional.

See the following sections for instructions on how to create projects in Impulse or nxpython:

Synthesis

Synthesis translates the design hardware description into a gate-level netlist using FPGA resources.

You can run the Synthesise step of the design flow in both Impulse and the nxpython environments (please refer to sections Synthesise and synthesise().

Place and Route

The Place and Route steps are performed on the synthesised design generated in the previous step.

In these steps, solutions for implementation are found to fit the user's design to the FPGA physical architecture:

  • The placement task computes the positions of the basic instance elements based on design and user-defined constraints

  • The routing process then assigns signals of the design to routing resources to successfully route all nets while achieving a given overall performance

 

 The Place and Route steps of design flow can be executed in both the Impulse and nxpython environments:

  •  See Place & Route for further information on how to launch corresponding states through Impulse

  • See place() and route() to learn how to launch the corresponding steps through command lines in the nxpython interface

Bitstream Generation

Bitstream data format is used to programme the FPGA.

Note: This step can only be launched after a Routing step has been successfully completed

Design Netlist Generation and Simulation

In nxpython, you can generate Post-Synthesis, Post-Place and Post-Route design netlists (Verilog or VHDL) which can be useful for simulation purposes (see section save(file)).

In Impulse, intermediate netlists are generated automatically

Third-party simulation tools can be used for design verification on Post-Synthesis, Place and Route files. Generated design netlists are provided along with the FPGA elements library.

This library is provided to the user in VHDL-protected format.

  • The library file can be found at the following directory path:

    $> /opt/NanoXplore/impulse/VERSION/share/modelsim/nxLibrary.vhdp

Static Timing Analysis

Static Timing Analysis (STA) can be performed by using its Timing analyser tool to analyse, debug, and validate the timing performance of the design.

This feature produces a detailed report on the timing characteristics of the design, i.e. timing domains in the design, longest/shortest paths in the domain, path delay, data arrival time, clock skew, etc.

Static Timing Analysis can be performed by Impulse (see section Static Timing Analysis) and nxpython (see section Static Timing Analysis related methods).

Welcome Screen

When you launch Impulse, a welcome screen opens offering quick access to startup tools.

The page is divided into the following areas:

  • Menu bar
    The main toolbar at top of the page displays the menus with a selection of available tools and options

  • Start
    The Start area at left gives you quick access to create or open projects:

    • Create New Project
      Opens the Project Creation Wizard which guides you through the steps to create a new project

    • Open Project
      Opens the File Manager to import your desired project into Impulse

    • Open Example Project
      Opens an example project with prefilled sample data and information to help become familiar with the tools and features in Impulse such as the Project Creation Wizard and Design Flow functionalities

Note: You can use your Example Project to run any step of the Design Flow

Tip: Click on the Run button in any step in the Design Flow to automatically run all previous steps

  • Recent
    The area at right of the page displays the last opened projects (use your mouse-wheel to scroll down the list of recent projects)

  • Learn
    Opens the Help and Documentation window with access to NX FPGA range datasheets, Impulse User Guide and beginner-level troubleshooting articles and FAQ’s

  • Python Console
    The console enables you to execute python commands in the GUI or view any python command that was previously executed in the interface

Click the maximise icon at right to expand or contract the window

Impulse Startup Page

Create New Project (Wizard)

To create your project and configure the environment of your choice:

  • Click Create New Project in the Start Panel at left, or

  • In the Menu bar at top, click File > New > Project

The resulting window is a Project Creation Wizard which guides you through the steps to create your project:

Step 1: Set Project Information

Define a project name and project location where files, logs, reports and data during the flow execution will be written:

  1. Type your desired name in the Project name field

  2. Type the path of your choice in the Project location field or click the Browse button at right to define a location for your project
    Tick the Use as Default Project Location checkbox to set it as default for all New Projects

  3. You can add an optional description

  4. Click the Next button at bottom-right to move on to step 2

Set Project Information

Step 2: Add Sources

Specify the Sources for your project (RTL files, netlist, Block Design, IP files, library, script):

  1. Click on the Add Files button under the Name and Location area, or
    Click on the Add Directories button to add directories containing your sources
    Note: You may need to use the scrollbar at right to navigate down to the buttons

  2. Tick the Copy Source Files to Project checkbox to create a duplicate copy of the selected sources in the project directory
    Note: Only the following file extensions are supported: sv, .vhdl, .vhd, .v, .vh, .svh and .py
    Note: The Name is the directory name of the folder where scripts, files and reports will be written

  3. Click Next at bottom-right to move to step 3 or, if you wish, you can also set Top Cell information at this point (see Optional sub-steps below)

Add Sources

(Optional) Set Top Cell Information

To enter the Top Cell Name or Library:

  1. Type the Top Cell Name and/or Top Cell Library directly in the corresponding fields at right, or
    Navigate to the file where the Top Cell Name is defined

  2. Right-click on the file and

  3. Click on the Select as Top Cell

  4. Click Next at bottom-right to move on to step 3 or, if you wish to do so, you can set optional Top Cell Parameters (see the section below)

Note: The Top Cell Name must be the name of the top cell declared in the top-level project HDL file

Note: The Top Cell Library is used to specify the library in which the top cell is defined (work library is defined by default)

Note: Both parameters can be modified in Project Settings after the project creation

Sources Added to Current Project

(Optional) Set Parameters of the Top Design Entity

You can also declare generic HDL parameters for selected top-level project design sources at this step:

  1. Click on the "+" button

  2. Fill in the Name field for the parameter and

  3. Enter a value in the Value field

  4. Click Next to proceed to step 3

Note: Only parameters with a valid Name and Value can be applied

You can add as many parameters as you require

top level

Set Top Cell information and HDL parameters

You can also use nxpython to assign generic parameters to the top level of the user design via the execution of python scripts. For further information on the assignment of parameters via nxpython, see the addParameter(name, value) or addParameters(parameters) commands

Step 3: Add Constraintsdrop-down

You can specify physical or timing constraints associated with the project if you have an existing constraints file in .sdc, .xdc or .py format.

Follow these steps:

  1. Click on the Add Files button (or Add Directory to add a folder)
    Note: You may need to use the scrollbar at right to navigate down to the buttons

  2. Browse and select your desired File/Directory and click Add

  3. Tick the Copy Constraints File to the Project checkbox to create a duplicate copy in the project directory

Specify a constraints file

Step 4: Select Devices

To select a device and associated package:

  1. Click on the down arrow at right of the Device or Package field to open the drop-down menu

  2. Click on the desired device and package

    • Repeat steps (1) and (2) for both the Device and the Package fields

  3. Click on the Next button at bottom to move on to step 5

Select the Device & package

Each of the NanoXplore FPGA devices (NG-Medium, NG-Large, NG-Ultra) can be fitted with different available packages or, in embedded versions, without the ring.

The different available device/package options are as follows:

Device

Available Packages

Device

Available Packages

NG-MEDIUM

CQFP-352, LGA-625, PBGA-625

NG-LARGE

CLGA-1752, FBGA-1752

NG-ULTRA

FF1760

Step 5: Project Summary

Check all the information is as you wish for your new project in the Project Summary screen.

  • If any of the settings need modification, click the Back button to return to the appropriate step and follow the instructions described in the previous sections

  • If all is as desired, click the Finish button to confirm the creation of your project and close the Project Creation Wizard

Project summary

Open Project

You can load projects at any step or sub-step phase of the design flow, as long as the project has been saved in .NYM format during execution of the corresponding step.

Impulse supports databases and projects to .NYM format only

To open an existing project:

  1. Click on Open Project in the welcome screen, or

    • Scroll through the Recent history at right and click to open your desired project, or

    • Click File > Open > Project

  2. Navigate to the .nym file of your choice

  3. Double-click the file or click to select your project and click the Open button

Load an existing project

Open an Example Project (Wizard)

Impulse also enables you to create new projects based on existing test cases which are bundled with the tool.

To do so do one of the following:

  • In the welcome screen, click Open an Example Project in the Start section at centre-left, or

  • In the main toolbar at top, click File > New > Project Example

Either option opens a simplified 4-step wizard which will guide you through the steps to create an example project:

Step 1: Select a Project Template

  1. Use your mouse wheel or cursor to select a Template from the available list and

  2. Click the Next button at bottom-right to move to Step 2

    Select a Project Template

Step 2: Select a Device

  1. Use the drop-down menus to select your device and associated package then

  2. Click the Next button at bottom-right to move to step 3

    Select a Device

Step 3: Set Project Information

  1. Type your desired name in the Project name field

  2. Type the path of your choice in the Project location field or click the Browse button at right to define the location for your project
    Tick the Use as Default Project Location checkbox to set your choice as default for all New Projects

  3. Click the Next button at bottom-right to move to step 4

    Set Project Information

Step 4: Project Summary

  1. Check the details in the Project Summary screen and and

  2. Click the Finish button at bottom to confirm creation of your Example Project, or

  3. Click the Back button to go back to any previous step and modify the details as desired

    Project Summary

Help Menu

The Help menu at far right of the main menu toolbar at top contains the following options:

  • Open Help and Documentation
    The Help and Documentation screen provides access to NX FPGA range datasheets, Impulse User Guide and beginner-level troubleshooting articles and FAQ’s

  • Find Technical Support
    Access to our Support Team for any questions about our products or licences

  • Report Issue
    Opens the NanoXplore Support Portal with access to Ticket Creation, Knowledge Base Articles, Release Notes, etc.)

  • Licence Manager
    Displays list of all features enabled by the NanoXplore licence file management tool

  • About Impulse
    Displays the current software version with the associated distribution information

Help Menu

Help and Documentation Screen

The Help and Documentation screen provides access to helpful resources laid out in 3 main areas:

  • DataSheet (top-left):

    • Datasheets for NanoXplore’s range of FPGA devices

      • Documents providing technical descriptions of the electronic components and features are included as well as instructions to use or configure them

  • Impulse User Guide (top-right)

  • Help & Troubleshooting

    • Simple troubleshooting, knowledge articles and FAQ’s for beginner-level users

Help & Troubleshooting

When you click on the Help > Open Help and Documentation option, the Help & Troubleshooting section at bottom of the page provides basic help and troubleshooting tips for beginners.

How To

 

The How To guides providestep-by-stepp instructions to perform basic operations such as project creation, I/O pad configuration or bitstream generation.

How To

Design Flow Overviews

These short guides are general functional descriptions of the Impulse Design Flow features, including conceptual presentations of the Synthesis, Place and Route processes.

Design Flow Overviews

Known Issues

These describe common issues and their workarounds, such as oversize, overflow behaviour or blending tile errors you may encounter during execution of the placing and routing phases.

Known issues

Licence Manager

The Licence Manager lists all features enabled under the current licence file, such as the various FPGA models or specific options and attributes available.

Licence Manager

About Impulse

Click on Help > About Impulse to view Licence information and Distribution details.

Note: This information is required when you contact NanoXplore Support with queries or issues

About Impulse

Edit Project

When you create or load a project or database, the main workspace opens with all available project management tools to edit, run, rerun any step of the NanoXplore Impulse design flow.

The Impulse interface is laid out as follows:

  • Main Menu Bar at top

  • Editor bar at left with the main editing and configuration tools:

    • Project Settings

    • STA Manager

    • IP Catalogue

    • I/O Attribute Editor

    • Floorplan

  • Project Sources Editor at centre-top of the screen

  • Design Flow Navigator at centre-bottom of the screen

  • The main area at top-right to configure the Editors

    • Click on a tool in the Editor bar to access the configuration settings in this area

  • The Python Console at bottom-right

Project Management Interface

Main Menu Bar

You can access all project management tools and editors through the horizontal menu at top:

  • File
    The File Menu contains the following options:

    • New
      Enables you to create new:

      • Projects/Example Projects

      • Constraint files, or

      • Design Source files

    • Open
      Enables you to open an existing project

    • Save Project/Save Project As
      Save your project in NYM format or in various other archive formats such as SDF, VHD or V

    • Generate SDF or Generate Netlist files at the corresponding design flow steps

    • Exit
      To close the application

File Menu

  • Edit
    Enables you to set User Preferences (click Apply to validate your changes then OK to close the preferences screen):

    • Environment Settings

      • Interface (Themes and Font size

      • Dialogue (enable/disable dialogue boxes)

      • Enable/diable Welcome Screen

      • Window Layout preferences

    • Shortcuts

      • Personalise your shortcut settings

    • Build Settings

      • Define various options for Build edition to select which default name for .nym file generation

    • Text Editor preferences

      • Select preferred editor along with associated font properties

    • Console Configuration

    • View

      • Edit navigation options related to the graphical interface

  • Project

    • Provides access to the Project Settings Menu (also avaiable via the corresponding Project Editor icon)

    • Enfables you to run Source Analysis in order to check design libraries dependencies and packages found in HDL sources of the current project and

    • Offers menu shortcuts to execute each of the design flow steps available to run Synthesis, Place and Route and to generate Bitstream

Project scrolling Menu

  • Tools

    • Lists all the provided tools within Impulse for the following:

      • Static Timing Analysis Manager

      • Constraints Editor

      • IP Catalogue NxCore Generator

      • IO Editor and

      • Floorplan View

Tools scrolling menu

  • Reports

    • Prints various reports concerning the project in a dedicated Impulse panel.
      Note: it is mandatory to execute NanoXplore flow steps through Impulse graphical interface to be able to print corresponding reports

  • Window

    • Enables you to select whether to view or hide panels of the Impulse interface like the Python console, the Flow navigator, Reports, Log, Messages, Editor, Sources template and Project sources

Window scrolling menu

  • Help

    • Edit Impulse default settings and check release and licence features information

Help scrolling menu

 

Editing Tools

The main Editors in the bar at left enable you to configure your project and device. Click on an editor to invoke the tool’s setting panel in the area at top-right.

Project Settings

The Project Settings editor enables you to configure project settings and edit parameters related to each step of the NanoXplore Design Flow:

Project Settings

Project Settings also enable you to change the default settings for the Synthesis, Place, Route and Bitstream steps:

Modify values of default flow options

Constraints Editor

The Constraints Editor identifies existing timing constraints that have been previously declared via python script or graphical execution through python console and saved in the database.

Constrains Editor list

The Constraints Editor includes the followin categories for timing constraints classifications:

  • Clock-related constraints such as:

    • CreateClock(), CreateGeneratedClock() and SetClockGroup()

  • Inputs

    • Lists SetInputDelay() constraints

  • Outputs

    • Lists SetOutputDelay() constraints

  • Exceptions

    • Regroups SetMulticyclePath(), SetFalsePath(), SetMaxDelay(), SetMinDelay() and SetCaseAnalysis() constraints

Example of constraints

The Constraint Editor respects the following syntax for declaration:

  • Mandatory arguments, which are marked with a red asterisk (“*”), and

  • Optional arguments, which are available for certain constraints by clicking on Add Parameters:

CreateClock() declaration

STA Manager

The STA Manager enables you to schedule or to directly launch a Static Timing Analysis after the Synthesis, Place or Route steps, depending on parameters such as;

  • Requested condition case scenario

  • Maximum number of violating paths or

  • Maximum slack upon analysis

STA Manager edition

IP Editor

The IP Editor provides graphical access to the IP Catalogue NxCore Generator provided with Impulse for IP configuration and generation concerning the provided list:

IP Catalog - NXcore

I/O Attribute Editor

The I/O Editor opens enables manual attribution or modification of placement of Inputs and Outputs in the selected device up to launch of the first step of Place. Once Place step 1/5 is launched, the location of Inputs and Outputs are defined either by user-defined constraints or automatically by the software.

I/O Config

The I/O Config tab shows how the input and output ports of the current design are mapped on specific pads with the following associated Pad Features:

  • HDL Name

  • Location

  • Standard

  • Drive

  • Weak Termination

  • Slew Rate

  • Termination

  • Input Delay Line

  • Output Delay Line

  • Differential

  • Termination Reference

  • Turbo

  • Signal Slope

  • Output Capacity

  • Register type

See the addPad(name, parameters) command section for further details on Pad features.

I/O Config I/O Attribute editor

Banks CKG Config

The Banks CKG Config tab shows:

  • Which banks with associated voltage are configured for the inputs/outputs of the Top Entity Design, and

  • Which CKG are used to control clock distribution into the design, including the location of the WFG which Impulse will use.

Bank & CKG configuration

Data available in the I/O Attribute Editor can be copied, exported to files or imported from files using the following icons:

Icon

Functionality

Icon

Functionality

Save Data to Project

Copy the table

Export Data to .PY or .CSV format

Import Data from .PY or .CSV file

Export I/O Data

You can export your I/O Config and Banks CKG Config data to an external file in python script (PY) format in comma-separated values (CSV) format.

  1. Click on the Export Data icon at left

  2. Navigate to the location of your choice in the File Manager

  3. Enter your desired file name in the Name field

  4. Click on the down arrow at bottom-right

  5. Select your your choice of file format in the drop-down menu

  6. Click the Save button

Import I/O Data

You can import an external set of pad assignments to configure rings either in via a dedicated python script or a CSV file.

Importing an external set of pad assignments can only be performed between execution of the Synthesis step and execution of first step of Place. Otherwise, the tool will provide automatic pad configuration to execute the Place & Route flow steps.

Floorplan Editor

Click Floorplan to open the graphical Floorplan design view at loaded .nym database status :

Floorplan view

Project Management

Once the multiple settings for the creation of the current project have been completed, user enters project management to launch design flow steps through Impulse panel.

Project management

The design flow steps are available for launching through either the dedicated Flow Navigator panel or the previously described scrolling Tools menu:

Flow Navigator

Each flow step in the Flow Navigator allows for editing associated flow options to the selected step before launching it, run either the whole Synthesis, Place & Route flow or a selected sub-step for each flow part, the possibility to generate netlist files, possibly SDF files after Route or to run a Static Timing analysis available for each flow step:

Design Flow step launching menu and options

Once one or several flow steps have been successfully executed and completed, you can check the Messages panel to look at reported Infos, Warnings & Errors, verify the step flow execution in the associated Log window.

Messages and Log reviewing

Users also have direct graphical access to reports generated at each flow step - labelled in green - in the Reports panel along the Flow navigator.

Report display in Impulse

Logging

All messages generated by the application such as generic information, warning and error messages or reports are stored into several log and report files, using either nxpython or Impulse.

When using nxpython the “logsPython” subdirectory is created into the working directory and log files are created inside it during flow execution. nxpython provides several commands to print error, warning or texting user defined messages (see section Export bitstream).

When using the GUI,the “logs” subdirectory is created into the working directory and log files and reports are saved inside.

Several log files are created:

general.log

contains all messages printed during the execution of nxmap steps: full tool log.

synthesise.log

contains all messages printed during the execution of the two synthesis steps. These information are also generated into the general.log file.

place.log

contains all messages printed during the execution of the five placement steps. These information are also generated into the general.log file.

route.log

contains all messages printed during the execution of the three routing steps. These information are also generated into the general.log file.

bitstream.log

contains all messages printed during the execution of the bitstream generation step. These information are also generated into the general.log file.

 

Report generation

Several reports are generated during the design processing to give information about resource utilization such as instances, ports, regions or timing.

Hdlfiles report

nxpython lists in hdlfiles.rpt report all HDL source files provided to Verific tool and also reports in which source file the Top Cell is declared.

Hdlanalysis report

nxpython lists in hdlanalysis.rpt report the messages issued by the Verific tool during the analysis of HDL source files. This files provides the name of all modules which have been compiled.

Fsmachines report

nxpython lists in fsmachines.rpt detailed information about finite state machines (FSM) identified in the design. If no FSM has been found, the file will be empty.

Hierarchy report

nxpython reports in hierarchy.rpt all instances for each module specifically kept by user with the command addModule(). By default, the file reports only the top level module, written ‘~’, if no module has been declared by user. See section addModule(model, instance, format) for description of this nxpython command and check carefully section Creating and handling regions for a complete and detailed example on the best way to keep modules.

Instances report

User has the possibility to generate instances report utilization of the design mapped on the current variant. For more information about generating instances report with nxpython, please refer to section reportInstances().

Latches report

nxpython lists in latches.rpt all latch elements synthesised during flow execution.

Maplogic report

nxpython prints in maplogic.rpt information issued during the mapping step for the standard logic processing such as flattening design, analyzing memory or analyzing dsp information. This files contains important information which can help for debug purpose.

Memories report

The memories.rpt file is organised into two sections:

  • Memory Cells analysis reports all memory elements used during synthesis step. Models and instance names are provided.

  • Memory Instances processing reports how memories are processed.

Operators report

The operators.rpt file is organised into two sections:

  • Operator Cells analysis reports all operators (adder, subtractor, multiplier, comparator, etc…) used during synthesis step. Models and instance names are provided.

  • Operator Instances processing reports how operators are transformed.

The first section is useful to identify names for commands.

The second section is useful to verify that addMappingDirective commands have been properly identified and taken into account by nxpython.

Ports report

User has the possibility to generate report on the ports found in HDL source and the ones manually set by user in the project. For more information about generating the Ports report with nxpython, please refer to section reportPorts().

Region report

User can generate report on the regions manually defined and distributed by user in the project. For more information about generating regions report with nxpython, please refer to section reportRegions().

Registers report

nxpython lists in registers.rpt all DFF elements without reset. It also indicates the number of DFF without HDL init info, which means without any initial context.

Timing report

The Timing analysis process creates several report files (.timing), each one containing information about a specific clock domain. For more information about the Timing report, refer to section Timing reports.

Unconnected report

nxpython prints in maplogic.rpt the list of unconnected nets processed during Synthesis flow execution. The information reported in this file depends on specific options of the setOptions() command (see section setOption(name, value) for more details): ManageUnconnectedSignals and ManageUnconnectedOutputs. By default, the severity of these two options is set to Error, which means Synthesis flow execution will stop if any incorrect net implementation is encountered. In this case, details of invalid nets will be reported in the report.

 

Floorplan exploration through selection commands

The floorplan view into Impulse allows graphical inspection through the synthesised design with a set of specific commands.

Floorplan Command menu

On the left of the floorplan panel, a vertical list of icons navigates easily through basic contextual actions such as zoom in, zoom out, scroll left, scroll right, scroll up and scroll down through the floorplan view.

On the right of the floorplan panel, a vertical list of icons enables or masks the following elements displayed in the floorplan view:

  • Show Lobes displays/masks the lobes of the selected FPGA variant

  • Show Global Aperture delimits the global aperture, representing the border limits where resources kept inside aperture boundaries should be used by the tool to place and map design elements (see setAperture(column1, row1, column2, row2) for manual command setting)

  • Show global focus displays/masks the focus, which is a target point placed in a TILE to define a central resource around where the HDL logic elements will be mapped and placed (see setFocus(column, row) for manual command setting)

  • Show Obstructions option displays obstructions, corresponding to a user-defined set of delimited FPGA resources inside boundaries which will not be used by the tool for mapping, placing and routing resources (see createObstruction(name, column1, row1, column2, row2) for manual command setting). These user-defined resources are removed from the design implementation

  • Show Regions displays Regions, identified as user-defined sets of delimited FPGA resources inside which specific HDL logic elements should be confined. See Creating and handing regions section for detailed explanations

  • Show net names on instances pin allows to hide or display net names attached to corresponding pins of registers, LUT elements

Net names displayed on instance pins

  • Show regions focus displays the focus point for each user-defined region

Show region focus

  • Show instances colour allows to modify the colours of design instances, also according to instance colour for logical elements constrained in regions to the same colour of the corresponding regions

a. Select nets

Select nets displays detailed information on single or multiple nets selected through the floorplan (fanout, id, number of instances connected to the net in user-defined regions):

Select nets

Select nets offers several criteria to parse elements:

By

Filters the type of architecture's element the net is connected to [Plane, Cover, Region, Zone, Instance or Pin]. Plane lists all nets of the design in the whole FPGA variant, Cover excludes nets from I/O

ring elements to keep elements in the matrix, Region restrains selected nets to defined region constraints, Zone restricts nets to selected TILE or CGB elements, Instance allows to list and select nets connected to any chosen instance (LUT, DFF, RAM, DSP, etc…) and Pin shows the net connected to current selected pin. 

Scope

Filters the nets of the design following specific criteria [All, Exterior, Interior, Incoming, Outgoing or Crossing]. Any lists all nets computed by the tool, Exterior lists only nets outside of the Fabric (connecting current IOs and CKG elements), Interior lists only nets inside the Fabric (connecting TILE and CGB elements), Incoming lists nets connecting input pads to Fabric elements, Outgoing lists nets connecting Fabric elements to output pads and Crossing lists nets coming from input pads and going to output pads.

Fanout

parses the number of nets of the design based on fanout criteria [All from 10+, 20+, 30+, 40+, 50+, 60+, 70+, 80+, 90+, 100+]

Sector

filters the nets of the design by number of sectors impacted [Any, None, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 1+, 2+, 3+, 4+, 5+, 6+, 7+, 8+, 9+, 10+]. The number of sectors in which Impulse will divide the nets depend on the size and the complexity of the design, which affect how the resources are spread and distributed around the sectors. For small designs, a small number of sectors could be enough as few logic elements need to be placed.

 

Once a group of net elements has been selected, the user has the ability to filter information with Combine and Select options of Selection section in order to navigate through matching elements specified in Name field.

The Name field allows to enter any string to filter corresponding net names, all finding results are listed below with matching net IDs and names. Various options of Combine and Select fields allow to choose one or several matching elements based on some criteria to be highlighted in the selection. Note that you can scale zoom to fit selected elements and clear all selected items in Name field with according options.

Detailed information for a selected net

User also has the Detail option which lists for a selected net its corresponding ID, name, the maximum fanout and the number of instances connected to this net through the floorplan.

b. Select paths

Select paths provides STA information on the selected paths and allows to select / show into the floorplan multiple paths with longest/shortest path plus clock domain selection:

Select path into floorplan

The Selection panel provides Combine and Select fields, allowing to choose one or several matching elements based on some criteria to be highlighted:

Select path detail

c. Edit Regions

Until Place 1/5 step flow, identified as the Prepared step, regions constraints can be manually edited through the floorplan view using Edit regions command.

To do so, select a defined region among the listed ones in the Selection panel and it will be highlighted in blank into the floorplan, allowing to expand or decrease left, right corners dimensions of the region at top and bottom.

Editing regions into the floorplan

Once the region dimensions have been edited, don’t forget to validate the changes by clicking on Apply constraints icon on the left of the floorplan.

Apply constraints to validate region changes

d. Region manager

Impulse provides a dedicated Region manager through the selection panel giving the possibility to perform through floorplan view the following actions:

  • Shows all Regions and Modules with their corresponding names, dimensions, locations, the partitioning of the resources included in the regions per type (LUT, DFF, Carry, DSP, Register File, RAM)

  • possibility to Create/Resize/Delete Region dynamically

  • Assigns Module to a new Region dynamically BUT creation from scratch of new Modules inside the Region manager is not possible

  • Clipboards and generates python file with all Region/Module/SetSIte/(DSP/RAM) location

Region manager interface

Combine Edit regions command with Regions manager functionalities to edit manually modify regions.

User can parse a list of Regions/Obstructions using this Region manager menu as it provides various actions through several right click dynamic menus:

  • outside existing regions, the logic is scattered into the fabric (identified as top level element with ‘~') and a right click on this gives access to General and Region '~’ menus

    • General allows to Edit Fabric dimensions inside which logic should be mapped, Create a Region or Create an Obstruction from scratch

    • Region ‘~’ allows to edit the dimensions of the top level '~’ region of the design, which represents by default the top level design and the logic inside it which is not constrained within user-defined regions

Regions General right click menu

 

Right Click → Select General → Edit Fabric to open the labelled editor and edit the dimensions of the fabric '~' as well as the relative focus point in order to modify the size of the matrix used by default to map resources

Edit fabric dimensions and focus point

Right Click → Select General → Create obstruction to open the labelled editor and create a user-defined obstruction with desired coordinates

Create Obstruction

If coordinates are missing or out of bounds, Impulse will display a red warning message and the obstruction creation will not be able to be validated until the coordinates are corrected

Right Click → Select General → Create Region to open the labelled editor and create a user-defined region with:

  • Your desired Name and colour tone

  • Ability to choose if the region is exclusive or not

  • Aperture coordinates, to define the location and size of the region

  • Anchor coordinates, for the focus point

Note: Anchor coordinates are placed in the middle of the fabric by default when Inherit focus checkbox is ticked

Create Region

Focus point placement when creating a region

  • Moving the mouse cursor on an existing region or module will give you access to the following menu using right click, you can edit characteristics of existing regions

Edit existing region

  • For existing regions that have previously been declared through nxpython methods in a dedicated script, logic instances have been constrained into these regions via module identification:

    • project.constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName)

    • user has the possibility through Right click → Module → Edit to move instance logic attached to a module from one region to another one

Edit module

→ for the associated module, select which region will used to constrain the associated logic instances

Edit module to change related logic region assignment

→ click on accept when the destination region is selected and you will observe in the floorplan that the logic instances colour identification will be modified to match the destination region colour

Logic instances moved into another region

→ don’t forget to click on Refresh button for the modifications to be taken into account into the floorplan panel

Refresh floorplan view once constraints and module are moved

  • user also has the possibility to import any constraint change performed from Impulse into nxpython equivalent commands for a python script overview : click on Copy constraints in the Region manager and paste the commands into the script

Copy constraints in a python script

Copy constraints can only import modifications of existing regions into contrainModule() commands.

If regions have been created through nxpython old methods (createRegion(), addModule(), confineModule()), Impulse won’t be able to make a Copy constraints and will generate an error.

Once you created or modified a region or an obstruction constraint, don’t forget to click on Apply constraints icon on the left side of floorplan panel to save the changes into the .nym database file.

 

e. Select instances

The Select instances command allows user to select one or several design instances based on different criteria and print corresponding name instance information in Selection panel.

When setting Command drop-down menu to Select instances, By drop-down menu to Plane and then clicking on the architecture representation in floorplan panel, all matching instances for the selected menu will be added in the Name field with the number of results found given current criteria. Selected items in Name list are highlighted in the floorplan panel upon Selection. Selection of instances can be adjusted with ID, Type, Location and Name arguments.

Select a design instance

When choosing Select instances, the available criteria is:

By

Selects the level among FPGA resources in which instances are listed and reported in Selection [Plane, Zone or Instance]. Plane option lists all instances used to map the current design on resources of the FPGA including instances locating inside CKG or iobanks for example. Region option parses instances to report following user-defined region constraints. Zone option reduce the scale of printed instances to the current selected zone, which can be an iobank, a CKG, a TILE, etc… Instance option lists instance name at lower level such as pads, PLLs, LUTs, DFFs, etc...

Category

Parses several levels of resources used to map logical elements such as LUT, RAM, DFF, Buffers, I/O configuration device, connecting elements between the matrix and the ring, etc…

 

When using Select instances command, user directly accesses information of the current selected instance detailed by Name, if the instance is part of a module or a region, its location in the design, potential configuration information depending of the kind of instances, etc…

Selection of a WFG instance

1. setSite management when select instances enable

When using command Select instances, setSite management - allows to select and move & place an instance into another site location - is available only at Place 1/5 step through the Selection panel: it allows to dynamically move and place a selected instance through Locking button.

Lock in target to place an instance into a different location

Select an instance to be moved in the floorplan, click on Locking to access the following possibilities:

  • Lock in target allows to select a target for the resource to be placed directly into the floorplan

    • In the above example, the instance name selected is GEN_HIER0|GEN_ROW[0].ROW_PIPE|pipe_reg_reg[11][I], originally placed by default into the TILE[15x6] as seen on the location field in the details part of Selection Panel

    • In the right part of Selection panel, dedicated to Locking actions with Unlock, Lock in place & Lock in target actions, the target location is dynamically adjusted as the cursor is moved into the floorplan

    • Once the target location is set for example in TILE[9x6], click on it through the floorplan and the instance will be automatically moved into the targeted resource and the location information in the instance list will be automatically updated as shown below

Lock in target instance placed into another resource

  • The target for a resource previously placed can be edited and modified using Unlock button:

    • the previous target placement will be relaxed

    • you can reuse Lock in target to change the target resource as desired

  • When you want to fix a target resource for an instance already defined by the tool in order to be kept through the whole Place & Route flow, click on Lock in place to permanently fix the target for the selected instance

2. Logic Cone manager when select instances enable

When using command Select instances, Logic Cone Manager - available in Tools panel near floorplan - allows for any selected instance - or group of instances as the By argument provides flexibility on the selection process - to visually identify either all incoming logic elements driving the inputs of this instance or all outgoing logic elements driven by this specific chosen instance; that way, the Logic Cone Manager lists all directly connected resources to the desired instance and calculate the delay from the instance to each type or resource connected to it.

Ingoing elements reported for a selected instance for 3 levels of logical depth

The Logic Cone Manager provides worstcase, bestcase and typical conditions choice through a scrolling button.

Reported elements to be analyse for the selected instance can be parsed by a desired type of pin : Clock, Load or Reset.

Useful options to use within the Logic Cone Manager are Depth and Max Depth arguments, which allow to extend from one selected elements analysed with their accumulated timing values to several level of logical instances to be shown and included in the graph. That way, a user can trace back multiple layers of instances back and forward to determine complex dependencies in data paths and how simplification for timing purpose could be useful.

outgoing elements reported for a selected instance for 3 levels of logical depth

g. Edit focus

The Edit focus command allows user to select which TILE resource Impulse must focus on for Place & Route flow steps, meaning Impulse will place various elements of the current design going to fabric resources around the focus point. By default, the focus point is placed in the middle of the FPGA but user can choose where to place it (following figure). Clicking on Apply will validate the choice of the TILE element chosen to place the focus point.

Edit focus

Once Place flow steps have been executed, resources of the current design are mapped around the chosen focus point.

Logic resources placed around the focus point

Selecting focus point placement in floorplan panel can only be performed launching Place flow

h. Edit aperture

The Edit aperture command allows user to edit the size of the aperture around the FPGA resources used for Place & Route steps. By default, the aperture size before launching Impulse flow steps is fitted to the fabric boundaries of the FPGA variant selected, excluding I/O ring.

The size of the aperture can be edited as much as needed (following figure) but user must keep in mind that the current design to be synthesised, placed & routed in the FPGA will have to use a minimum of resources to be correctly mapped. In other words, user can’t define a size for aperture which is too small to map the full design requested otherwise Impulse will generate an error during Place step, preventing the tool to execute all subsequent steps for current design.

Edit aperture

As long as aperture is fitted to design needs, Impulse will be able to place design elements among resources restricted with aperture size (following figure).

Logic resources placed after defined an accurate aperture

i. View obstructions

The View obstructions command allows user to see obstructions created among the resources of the FPGA. Obstructions will be recognized by Impulse as forbidden resources excluded from elements used during flow execution various steps to place and route the logic instances of the design.

Obstructions can be created through nxpython until the execution of Place flow to be taken into account with the dedicated command createObstructiin(). Here is a brief example with some nxpython command lines:

project = createProject("/path/to/working/directory/") project.createObstruction('OBSTRUC1', 4, 6, 5, 6) project.createObstruction('OBSTRUC2', 13, 6, 14, 6) project.save('native.nym') ## obstructions created and saved before launching synthesis steps

 

Obstructions can only be created before launching Place flow during the execution of global steps. Obstructions created during next and further flow steps will not be accepted by the tool.

 

Creating and handling regions

nxpython provides a set of commands that allows to create specific regions among the current FPGA target variant in which some user-defined logic can be restricted during Place and Route execution steps. The purpose of this section is to help user understanding the mechanisms behind the creation of regions through a complete example. Two commands have been designed for this purpose:

  • constrainModule()

  • constrainPath()

1. constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

First, user has to identify which particular logic resources will have to be specifically restricted into a region for timing optimization purpose. NanoXplore design flow through nxpython tool provides a specific approach that consists in gathering logic elements and resources into identified modules through the existing design hierarchy and then confine these modules within regions bounded to desired FPGA resources.

constrainModule() has been implemented to create region constraints in order to confine logic instances inside with the following purpose:

  • Simplifying logic identification inside the design

  • Using only information provided in hierarchy.rpt without handling regular expression pattern detection

  • Reduce the number of commands used for region constraining from three dedicated command for the previous process to only one efficient method easy to use for the user

 

After a first run execution of the synthesis flow step in Impulse, hierarchy.rpt provides all hierarchy design information needed to define constrainModule() commands for the design:

  • HDL Modules Hierarchy Detail section

HDL Modules Hierarchy

  • Default User module detection in the report will only report ‘Module ~’, which is the notation representing the top level HDL module hierarchy when no constraint has been set

  • Note this report also provides a precise repartition of the design mapped on the different components of the fabric and Clock generator blocks (CKG):

    • 4-LUT, DFF, XLUT

    • Carry

    • RFB

    • cross domain clock, clock buffer, clock switch

    • DSP, RAM (CGB components)

    • WFG, PLL (CKG components)

Classic examples using hierarchy.rpt to identify logic instances to be constrained into regions ( ‘|->’ is not mandatory but is accepted for hierarchy argument):

project = createProject() project.constrainModule('|-> INTERP_x2_20M_to_40M [ INT_20_40 ]', 'INT_20_40_MOD', 'Hard', 5, 4, 2, 3, 'INT_20_40', False) project.constrainModule('|-> INTERP_x2_40M_to_80M [ INT_40_80 ]', 'INT_40_80_MOD', 'Hard', 7, 4, 2, 3, 'INT_40_80', False) project.constrainModule('|-> SRL_MEM_SYMMETRY_EVEN(X834F2609) [ FIR_MF|MEM|EVEN.MLT.NR[0].FIRST.FIRST_EVEN ]', 'FIRST_EVEN_MOD', 'Hard', 1, 10, 1, 1, 'FIRST_EV_1_R', False) project.constrainModule('|-> SRL_MEM_SYMMETRY_EVEN(X30E78A1F) [ FIR_MF|MEM|EVEN.MLT.NR[1].OTHE.OTH_EVEN ]', 'OTH_EV_1', 'Hard', 2, 10, 1, 1, 'OTH_EV_1_R', False) project.constrainModule('|-> nx#NX_DSP_SPLIT(X2C70EFCA) [ FIR_MF|GEN_DSP[0].DSP|G_INST.DSP ]', 'DSP_MOD_1’, Hard', 1, 8, 1, 1, 'DSP_SPLIT_1’, False) project.constrainModule('|-> nx#NX_DSP_SPLIT(X2C70EFCA) [ FIR_MF|GEN_DSP[2].DSP|G_INST.DSP ]', 'DSP_MOD_3', 'Soft', 3, 8, 1, 2, 'DSP_SPLIT_3', True ) project.save('/rtl/native.nym') project.synthesise(): project.save('/rtl/synthesised.nym')

 

Once synthesise step of the flow is executed using region constraints from constrainModule() commands, hierarchy.rpt provides useful information to check preliminary constraints as written by user before flow implementation - specified by Unused (Not yet assigned) - and after usage by the tool for execution.

HDL Module usage with constraints

If the syntax of some constraints is wrong - assuming that if hierarchy argument of constrainModule() is not matching an existing model instance - those will be labelled as unused by Impulse.

A Usage labelled ‘unused’ implies the corresponding constrainModule() cannot be applied to the design flow.

In hierarchy.rpt, successfully created modules by constraints are listed with the list of resources mobilized for each one of the modules.

Successful Module constraints

Before opening the floorplan panel of Impulse, one can easily check how many hierarchy instances are gathered into newly created regions by checking the HDL module hierarchy section of hierarchy.rpt:

HDL hierarchy detail after creation of region constraints

And finally, a look a floorplan panel of Impulse offers visual glimpse on how region constraints with the associated logic instances placed inside are placed in delimited resources with colour codes:

Various regions constraints successfully implemented

2. constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

constrainPath() provides even more precision in identifying logic instances aimed for placement by specifying all elements between selected registers to be confined into a specific region.

This method takes in argument a list of source and destination registers between which all logic elements (LUT, carry) will be constrained into a region specified by the coordinates provided with the dedicated arguments.

constrainPath() allows to identify and constrain at register name level whereas constrainModule() is used to constrain at hierarchical instance levels described in hierarchy.rpt file, so offers more flexibility to identify and confine smaller parts of the design in case touchy timing paths require precise placement.

Constraining resources between source and target registers

Registers provided as source and target arguments will also be part of the logic constrained and included into the region; DSP and memory macros - containing pipeline registers - such as RAM and Register Files are also identified as source and target arguments for constrainPath().

During nxpython command execution, constrainPath() has priority over constrainModule() and can be used to constrain specific logic between registers inside a region previously created with constrainModule().

Some examples of command to use constrainPath():

project = createProject() project.constrainPath(['i_cpt_0|s_cpt_out_reg*'],['i_cpt_1|s_cpt_out_reg*'],'cpt0_to_1_module','Soft',9,6,2,3,'cpt0_to_1_region',False) project.constrainPath(['i_cpt_1|s_cpt_out_reg*'],['i_cpt_2|s_cpt_out_reg*'],'cpt1_to_2_module','Soft',11,6,2,3,'cpt1_to_2_region',True) project.constrainPath(['i_cpt_2|s_cpt_out_reg[0]'],['i_cpt_3|s_cpt_out_reg[0]'],'cpt2_to_3_module',13,6,2,3,'cpt2_to_3_region') project.save('/rtl/native.nym') project.synthesise(): project.save('/rtl/synthesised.nym')

constrainPath() and constrainModule() use

 

Attributes

Attributes can be set to signals in the design code in order to tag this signal and affect some configurations.

Nx_init

nx_init attribute is used to initialize an inferred memory with a file.

Example:

attribute NX_INIT: string; attribute NX_INIT of s_mem: signal is "../initdata.nx";

Nx_port

nx_port attribute is used to configure an IO pad.

Example:

attribute NX_PORT: string; attribute NX_PORT of RST : signal is "(location= IOB11_D09P, turbo= True, inputSignalSlope=20)"; attribute NX_PORT of cout0_a : signal is "[ all :( turbo=True, standard= LVCMOS, inputSignalSlope= 20)" & "; 0 : ( location= IOB5_D01P, standard= LVCMOS, drive= 2mA )" & "; 1 : ( location= IOB5_D01N, standard= LVCMOS, drive= 4mA )" & "; 2 : ( location= IOB5_D02P, standard= LVCMOS, drive= 8mA )" & "; 3 : ( location= IOB5_D02N, standard= LVCMOS, drive= 16mA )]";

Nx_use

nx_use attribute is used to add a mapping directive to a memory or an operator.

Example:

attribute NX_USE: string; attribute NX_USE of s_mem_0: signal is "RAM"; attribute NX_USE of mult: signal is "NX_DSP";

Syn_keep

syn_keep or syn_noprune attributes are used to set a net as mandatory disabling signal optimization.

Example:

attribute syn_keep: boolean; attribute syn_keep of s_keep_it_0: signal is true; attribute syn_noprune: boolean; attribute syn_noprune of s_keep_it_1: signal is true;

Syn_preserve

syn_preserve attribute is used to set a register as mandatory disabling signal optimization.

Example:

attribute syn_preserve: boolean; attribute syn_preserve of hier_in_row_p2: signal is true;

 

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