Training Package - Application Note - Ip
- Kévin Chopier
Ip
CrossDomain
Description:
The user can cross clock domain properly thanks to NanoXplore IP. Implemented IP are:
IP_CDC: simple signal data clock domain crossing
FIFO: data bus clock domain crossing
IP_CDC is included in NanoXplore release.
FIFO IP is generated with NxCore software.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | Yes |
Attributes |
|
IP | IP_CDC FIFO |
Methods | addIp |
Table: Ip CrossDomain environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in progress.rpt that soft IP are synthesized.
Simulation check: Check output of CDC and FIFO IP.
Board check: No board purpose for this testcase.
Ddr2Dfi
Description:
The user can interface with a DDR2 memory thanks to the NanoXplore DDR2 DFI IP.
This is only an IP for the physical interface and the DDR2 controller is not provided. For instance, contact 3D+ to get a DDR2 Controller.
It is a hardware IP as it configures IO and implement PLL and WFG from CKG.
The user has to adapt the pinout file to fit to the project needs.
For additional information, please have a look at NanoXplore_DDR2_DFI_IP documentation available on DDR2 DFI IP.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | IP_DFI |
Methods | addIp |
Table: Ip Ddr2Dfi environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in progress.rpt that the IP is synthesized.
Simulation check: No simulation environment is available for this testcase.
Board check: Switches and leds allow to control and receive data.
ExportIp
Description:
The user can generate an IP with its design and reuse it in a top project using exportAsIPCore NXpython method.
Exported IP can be genereted encrypted or not depending on set option.
Hereafter an example for this method:
p.exportAsIPCore('../hierarchical_ip.vhd', {'coreName': 'hierarchical','encrypt':'All'})
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | ExportAsIPCore |
Table: Ip ExportIp environment
Option: There is one option to check the impact of this constraint:
No option: RTL files are directly used.
ExportIp: RTL files are used to generate an encrypted IP and this IP is reused to generate a new project.
NanoXmap check: After project launching, the user can check in hdlfiles.rpt that IP is used to generate the new project.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
HsslEsistream
Description:
The user can interface with HSSL links thanks to the NanoXplore HSSL macro cell.
The HSSL configuration is compliant with ESI stream protocol.
The implemented design is an external loopback.
The architecture of wrapper_hssl_esistream block is described as below :
Signal | Type | Description |
hssl_clock_i | In | HSSL clock input |
reset_n | In | Global reset for the application |
pma_ck_ref_i | In | Reference clock (for NG-LARGE DevKit, it is coming from an external oscillator (ESIstream 156MHz)) |
tx_rst_n | Out | Transmitter reset |
usr_tx_busy_o | Out | Asserted when reset is in progress |
usr_tx_esistream_sync_i | In | End of multiframe ESIstream synchronization input signal |
usr_tx_ctrl_driver_pwrdwn_i | In | TX driver is deactivated when asserted; output is at high impedance |
usr_tx_data_i | In | 8 data symbols to be sent by TX |
hssl_clock_o | Out | HSSL user clock sent to the fabric (48MHz) |
usr_pll_lock_o | Out | ‘1’: PMA CDR Pll is locked (Async Signal) |
usr_rx_ctrl_not_in_table_o | Out | Indicates presence of a not in table error in the corresponding symbol, when asserted. |
usr_rx_ctrl_dscr_null_o | Out | Indicates which octet is a lane character. The block marks where /A/ character was received, before replacing it based on the character replacement rules. |
usr_rx_ctrl_char_is_aligned_o | Out | Asserted when symbol is aligned. |
usr_rx_busy_o | Out | Asserted when reset is in progress. |
usr_rx_pll_lock_o | Out | Asserted when RX PLL is locked. |
usr_rx_esistream_sync_o | Out | End of multiframe ESIstream synchronization output signal |
Environment:
Here after the table of compliances for this testcase.
Variant | NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_HSSL_L_FULL |
Methods | createClock |
Table: Ip HsslEsistream environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI macro cells are observable in the GUI.
Simulation check: No simulation environment is available for this testcase.
Board check: The user can program the NanoXplore NG-LARGE Evaluation Board with the following steps:
1- Launch the script with the following command:
NXpython script_NG-LARGE.py-> Make sure the bitstream is successfully generated.
2- Configure the FPGA with the following command:
nxbase2_cli NXmap/switch_NG-LARGE/bitstream.nxb-> Make sure the LED named "Ready" on the Devkit is turned on
3- Check the following points :
ERROR FLAG deactivated on J15 PIN1
HSSL_CLK at 48MHz on J15 PIN3
ESISTREAM SYNC RX/TX activated on J15 PIN 5
RX_PLL_LOCKED activated on J15 PIN7
PMA RX CLOCK on on J15 PIN13
R5BootOutTcm
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
R5 Core uses Axi Master port to boot.
Hereafter the architecture of the design:
Environment:
Here after the table of compliances for this testcase.
Variant | NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_R5_L_WRAP NX_SCOPE NX_PLL NX_WFG |
Methods | addMemoryInitialization addMappingDirective |
Table: Ip R5BootOutTcm environment
Option: Only mainADD option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI that macro cell is observable.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
R5AxiSlave
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
R5 Core uses Axi Slave port to boot on TCM memory.
Hereafter the architecture of the design:
Environment:
Here after the table of compliances for this testcase.
Variant | NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_R5_L_WRAP NX_SCOPE NX_PLL NX_WFG |
Methods | addMemoryInitialization addMappingDirective |
Table: Ip R5AxiSlave environment
Option: Only mainADD option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI that macro cell is observable.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
R5Jtag
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
R5 Core uses DAP port to boot on TCM memory.
Hereafter the architecture of the design:
Environment:
Here after the table of compliances for this testcase.
Variant | NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_R5_L_WRAP |
Methods |
|
Table: Ip R5Jtag environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI that macro cell is observable.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
Serdes
Description:
The user can send and receive data at high speed thanks to the NanoXplore SERDES macro cells.
SERDES IP can only be implemented in complex banks.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_SER NX_DES NX_WFG |
Methods |
|
Table: Ip Serdes environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI that macro cell is observable.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
SpacewireLoopback
Description:
The user can communicate with Spacewire link thanks to the NanoXplore SpaceWire macro cell.
SpaceWire IP can only be implemented in complex banks.
The implemented design is an external loopback.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | IP_SPW_BANK IP_FIFO_part NX_PLL NX_WFG |
Methods | addIp |
Table: Ip SpacewireLoopback environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI that macro cells are observable.
Simulation check: No simulation environment is available for this testcase.
Board check: The user can program the NanoXplore Evaluation Boards with the following steps:
1- Launch the script with the following command:
-> Make sure the bitstream is successfully generated.
2- Configure the FPGA with the following command:
-> Make sure the LED named "Ready" on the Devkit is turned on
3- Check data is displayed on LED.
SpacewireRoadmap
Description:
The user can communicate with Spacewire link and Roadmap protocol thanks to the NanoXplore SpaceWire macro cell.
SpaceWire Roadmap IP from Service bank can be used only in case of not used for configuration in Slave Spacewire mode.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_PLL NX_WFG |
Methods |
|
Table: Ip SpacewireRoadmap environment
Option: No option is available for this testcase.
NanoXmap check: After project launching, the user can check in the GUI connections with SPW interface.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
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