Static Timing Analysis (STA)

• Nanoxplore Design Contraints (NxDC) : The following python methods are compliant with NxMap:

  • addReportPath() : this method gives the shortest and the longest delays of a path

  • addReportPath() supports source & target arguments using new getPin() method

  • removeConstraints() allows to remove a design constraint from the current project

GUI

• New Impulse interface

  • Constraints editor icon to create, import and review timing constraints

  • STA manager now allows to schedule related flow step launching of analysis

  • NXcore IP catalog now available for IP configuration & generation through the GUI:

    • IP updates can be directly added to an existing software release

  • Command:

    • Select Instance :

      • Logic Cone Manager tool created to investigate logic cones with associated timings

  • Python console can source full python scripts

  • Each FPGA variant provides its own available packages for selection during project creation

  • Help section incorporates embedded documentations

Python method

• addHSSLLocation(): set the location spot in which a HSSL should be set

• getProject(): returns the project object

• removeSoftModules(): removes all HDL soft modules from a project

• getAnalyzer(): returns the current analyzer associated to the project to manage STA

• printHierInfo(): prints the detailed hierarchy of a project with the module matched and all instances per module

• getHierInfo(): returns the detailed hierarchy into a dictionary variable

• reportDesignComplexity(): reports the design complexity indicating the logic depth for all paths of the design and illustrates it with a chart in HTML format

• clearFabricPrePlacedConstraints(): clears all preplacing constraints for fabric elements

• add 'DisableRegisterMergeInDspForAdd' option to tisable merge of registers in DSP when used as adder

Report

• progress.rpt : I/O array now describes Registered parameter (Asked:Applied) configured for a pad

NXCore

• spacewire_roadmap IP added in the catalog

• spacewire_roadmap_iom added in the catalog : XOR configuration in complex bank to generate SPW recovery clock (available in NG-MEDIUM & NG-LARGE)

Bug

• NXcore: spw_rx generation issue fixed

• SDF : added missing relation for sdf rfb (RA6 to O*)

• Backannoted netlist : additional use models for DSP macros implemented

• getClockNet() nxpython method cannot be used before Prepare step (Place 1/5)