Table of Content

List of figures

List of tables

Introduction

Scope of the Document

The aim of this document is to define and analyze the Brave FPGA radiation tests.

Applicable and Reference Document

Applicable Documents (ADs)

[AD 1] SINGLE EVENT EFFECTS TEST METHOD AND. GUIDELINES. ESCC Basic Specification No. 25100.

Reference Documents (RDs)

[RD 1] SEL simulation, Space & Defense BL, NG FPGA, V1.0, 24/11/15

[RD 2] ST User Manual - THSENS_B_CMOS065LP_50A_um, 1.0, February 2014

[RD 3] https://creme.isde.vanderbilt.edu/CREME-MC/help/rpp-method

[RD 4] ESA_D50_HardeningStrategy

List of Acronyms and Abbreviations

Definitions

Device Description

Chip architecture

The device is composed of a central fabric embedding the programmable logic, RAM and DSP blocks, and peripheral I/O buffers. The fabric is covered with a grid of high level functional blocks interleaved with interconnect structures providing routing resources to realize the connections within the fabric and to the peripheral I/O buffers. The programmable logic resources are arranged in a hierarchical structure called a TILE with a specific local interconnect network. The I/O buffers are arranged into multiple banks as depicted on the figure below.

Figure 1: Device Floor Plan

FPGA Block

The following table summarize the main functional block of the NG_MEDIUM FPGA.

Table 1 : NG MEDIMUM Resources

Configuration Memory access

Access to the FPGA block is done through a synchronous 16-bit peripheral interface to the "Loader" function. The Loader function is controlled by an asynchronous reset signal and a programming clock (nominal 50 MHz), and communicates through a 16-bit bidirectional bus.

Technology

The chip is implemented on ST 65nm technology and has been designed with the SPACE PDK extensions and the hardened SPACE libraries.

The chip manufacturer is ST Microelectronics. The chip has been processed in Crolles facility.

Die Information:

Die size: 15.30mm x 10.96mm

• Passivation + metal stack thickness: < 40 µm

• Total passivation thickness (SiO + SiN) < 1µm,

• Metal stack max (7 metal + Alucap) + InterDiel is 7µm

Therefore the total material thickness to reach active region is less than 8µm.

Package Information:

The chip is packaged in a CLGA-625:

Dimensions: 29mm x 29mm x 3.4mm

Pin count: 625

Ball pitch: 1.0mm

Figure 2: Package Picture

Brave chip power supplies

Core power is 1.2V, I/O power is 2.5V.

Table 2: Power Supply Description

Test Hardware

The test hardware is composed of two boards:

A control board, used as a base board and supporting the control, supply and interface hardware.

A mezzanine board supporting the device to be tested.

Figure 3: Test Board Picture

Control board hardware overview

The control board is connected through USB to the host computer, and uses a single 12V main power supply. It is built around a Cypress EzUsb microcontroller and a companion FPGA (Spartan 6SLX25), and integrates:

Its own power supplies from main +12V.

Four latch-up protected power supplies modules providing four target supply rails.

Power supplies voltage and current measurement instrumentation.

Control for heaters to raise device temperature.

Two fabric clock generators.

Multi-chip target board hardware overview

Power supplies

The control board provides 4 latch up protected power supplies for the target board.

The latch up protected power supplies are realized around a 2-amp integrated switching regulator controlled by the central FPGA. Control includes a +/- 10% voltage adjustment using a digital potentiometer. The power supply current, measured across a sense resistor, is applied to a 12-bit, 3 MSp/s serial A/D converter continuously read by the FPGA.

Figure 4: Power Supply Schematic

Realized in the FPGA, the trigger conditions and response time are completely programmable, with a minimum response time close to 1 µs.

Upon detection of an abnormal current rise:

The switching regulator is disabled.

The target board is cutoff from the power supply by a MOSFET pass transistor, and another MOSFET transistor switches the supply to a dummy resistive load.

The target board power rail is grounded by another MOSFET transistor.

The latch up protected power supply provides two 50 Ω SMA outputs:

• an oscilloscope trigger

• a current monitoring output.

Power supply measurements

The NXBASE board features several A/D converters for power supplies supervision:

For each latch up protected supply, 2 high speed SAR A/D converters for the voltage and the current measured across a 0.1Ω sense resistor, with a gain of 10. This last measurement is part of the protection scheme.

A slow, high precision delta-sigma A/D converter (AD7714) with input multiplexors gives a precise measurement of the board local supply voltages, and the latch up protected supplies voltage and current.

All measurements are monitored and displayed on the PC control application. The Figure 6 shows the monitoring of a latch up event.

Figure 5: Power Supply Monitoring (Latch up)

Note: Latch up is simulated by a MOSFET shorting VDD and GND.

Latch up Control

The latch up control circuitry is fully programmable with the following parameters:

In addition, the latch up detection is inhibited during power on cycles to prevent any false detection triggered by capacitance charging current or any device induced effects.

Figure 6: Latch up Detection

Device Temperature Measure

The temperature measure uses the on die thermal sensors which have an accuracy of 4°C.

Control Application

The hardware is connected by a USB 2.0 link to a control PC running one of the application programs:

• NxBase: A program with a GUI developed with the Python language with USB, QT4 and matplotlib packages.

• NxBase2: A program developed in the Python language with a command line interface and scripting features.

Both programs include:

• An API to control the power supplies.

• An API to control and monitor the power currents.

• An API to control the device temperature.

• An API to access the FPGA block.

• An API to control the ion beam shutter.

The chosen test software calls API functions to:

• Download patterns in the configuration memory.

• Open and close the beam shutter.

• Read back the configuration memory.

• Store and correct potential SEU.

Figure 7: Graphical User Interface

Test

Sample preparation

Delidding of the chip is done, in order to directly irradiate the die.

Figure 8 Opened chip

Irradiation sites

Heavy Ions tests

The heavy ions radiation tests were performed at the Cyclotron Resource Centre located in the Université Catholique de Louvain (UCL) at Louvain-la-Neuve, Belgium.

We used their Heavy Ion Irradiation Facility (HIF).

Figure 9: UCL HIF Equipment

Ion beam specification

The ion beam cocktail below is used.

Table 3: High Penetration Ions

The beam flux is variable between a few particles/s.cm² and 10⁴ particles/s.cm². The beam flux can be modified from the user station, this is done with injection grids (for a constant attenuation factor) or by inflector bias variations (for intermediates values). The Homogeneity is ± 5 % on a 25 mm diameter.

Protons tests

The proton radiation tests were performed at the Paul Sherrer Institute (PSI) at Villigen, Switzerland.

We used their Heavy Proton Irradiation Facility (PIF).

Figure 10: PSI PIF Equipment

Proton beam specification

The usable energies span from 6MeV up to 230MeV in a quasi-continuous way. The Homogeneity is ± 5 % on a 25 mm diameter.

Tests of SEU on configuration memory and user memory

The SEU is performed at room temperature, which is measured. Supplies are at their min value (-10%):

• VDD1V2 Core supply 1.08V at the input of the chip; since no voltage sensor is used the core supply is 1.045V inside the chip.

• VDDIO/VDD3V3 2.97V

SEU test is done up to 10⁶p/cm^-2 fluence.

Two tests are done for configuration and user memory.

Cell under test

The table below give the configurable cell under test, the occurrence in the fabric and the number of configuration of each one:

Table 4: Occurrence of configurable cell in the macro

User memory:

• 56 DPRAM ST_DPHD_2048x24m4_b with or without ECC:

  • 2K (K=1024) * 24 without ECC

  • 2K (K=1024) * 18 bit with ECC (6-bit ECC)

• Regfile only with ECC:

  • 64 * (22 bits: 16 bits with 6-bit ECC)

Test protocol for each LET/energy and angles

SEU is detected by loading a chess board pattern (even address: 010101…, odd address: 101010…) for even column and the inverted chess board for odd column. In order to prevent any SEFI caused by the surrounding logic, initialization and read back are performed with the shutter closed. For each flip, the software stores the word address and bit location in the word.

For the DPRAM radiative test, a zero pattern of 18 bit with 6 bit ECC is written at each 24bit word of the DPRAM. A design is mapped in a tile to repeat it for each CGB: this design read each of the 2k (11bit) address at each cycle and correct the previous address. The error that are detected or that can be corrected by ECC are counted. Since this application for test is running under radiation, this is hardened by using TMR on DFF and logic except the bit error at the output of the ECC bloc.

The shutter is controlled by the application software, the test measures the total time when the shutter is open. Since no particles are counted when the shutter is off, the fluence measured with the detector reflects exactly the fluence received by the chip under test.

During SEU test, the supply current is continuously monitored to mitigate any SEL.

A semi static test is performed with SEU accumulation over a period of 30s and memory scrubbing. The sequence is:

• Close shutter

• Initialize memory with chessboard pattern

• Open the shutter and start timer

• Every 30s (single sequence):

• Close shutter and stop timer

• Wait 2s

• Check and correct memory (Scrubbing).

• Store SEU

• Open shutter and restart timer

• Stop when 10⁶cm^-2 total fluence is reached.

For protons test, not shutter is available. The particle beam is controlled using the provided command software. The sequence as described below. It is repeated until the desired fluence is reached.

• Stop the particle beam

• Initialize memory with chessboard pattern

• Start the particle for a given fluence

• Wait for the requested fluence (this will automatically stop the particle beam)

• Wait 10s

• Check and correct memory (Scrubbing).

• Store SEU

Error counting and cross-section

Cross_section[cell][state]= (SEU[cell][state] / number[cell][state])/fluence

Cross_section[cell][state]= cross-section for a given type of cell with an initial state

number[cell][state] = number of cells for a given type of cell with an initial state

SEU[cell][state] = number of counted SEU for a given type of cell with an initial state

Test of SEU on dff_cell_core latches, SET on clock tree

The SEU is performed at room temperature, which is measured. Supply are at their min value (-10%):

VDD1V2 Core supply 1.08V at the input of the chip; since no voltage sensor is used the core supply is 1.045V inside the chip.

SEU test is done up to 10⁶p/cm^-2 fluence.

Cell under test

The occurrence of each cell in the fabric is provide by the table below.

Table 5: Occurrence of DFF, clock buffer and matrix

FPGA configuration for test

The dff_cell_core (2 latches) shall be studied for every state of input, output and clock. So that each 1/8 of the dff_cell are set in each combination of states:

• Tow static clock staying at 0 and 1 are provided at the input of the fabric clock tree. The left and right side are driven with these 0 and 1 static clock.

• Each Section are programmed as in the table below where a LUT of the first table is connected with the DFF at the same position in the second table

Table 6: LUT programming and DFF context

In order to have the same number of master and slave latch memorizing, PosEdge configuration is set at the same value in every dff_cell. Seq is set to 1, in order to enable the clock provided by the clock tree.

Remark: A SEU on Seq when CLK0/1=1 or a SEU on PosEdge make the memorizing latch to flip if Input ≠ Output.

A dff_cell input (LUT) is applied by setting all the configuration bit of the upstream LUT to the required value, with the bit AuxIn set to 0 and Len0:3 set to 1 so that the LUT output is the input of the dff_cell.

The error due to SET on the reset path inside the dff_cell_core was made negligible by design, the possible sources of SET on reset could come from the system tree on the reset path and a bit flip of dff_cell configuration bit Ren0:2, Sync. The reset tree has the same architecture as clock tree, so the SEU due to SET on RESET can be deduced from the clock tree study. To disable reset from system reset tree Ren0:2, Sync is set to 1, so that the reset value is force to 0 and the SEU due to reset SET only come from a bit flip of Ren0:2 or Sync. Then to make the SEU on reset negligible all the reset input RST SYS0:5 are set to 0, so that a SEU on Ren0:2 or Sync don’t affect the reset value that remains at 0.

Finally, the output that is the data memorized in the latch is set by writing the context of the dff_cell. Its reading is done by a context reading of the dff_cell, so that AuxOut values can be arbitrarily chosen.

Table 7: DFF configuration/input condition for radiative test

When Input = Output. SEU are due exclusively to SET on latch.

When Input ≠ Output the possible SEU come from SEU on latch or SET on clock tree.

In order to have enough statistic on mtx and lowskew, every mtx on clock path to dff_cell drive 32 dff_cell and 16 dff_cell with Input ≠ Output, so that it is also possible to discriminate if the SEU come from a dff_cell or the amount mtx. Furthermore, in order to discriminate the error due to each level of mtx or multiple output lowskew with their downstream one output lowskew, each mtx clock input shall drive 2 output mtx bit. The clock tree is divided into group, a group begin after another and end at the cell that drives 2 or more other downstream clock trees. The groups are numbered from the dff_cell and are called CLOCK_GROUP[0:x]. Thus, the error can be counted for each types of group, by finding the most amount CLOCK_GROUP that made flip all the dff_cell driven by it. Considering that the clock mapping is done as follow.

Figure 11: Clock mapping

Test protocol for each LET/energy and angles

This test follows the same protocol as 5.5.2 Test protocol for each LET/energy and angles

Error counting and cross-section

The cross_section of dff latches and CLOCK_GROUP can be extracted with this algorithm example:

CLOCK_GROUP_SET[0:x][0:1] = 0; #count the SET for each clock group level and clock state

Total_ CLOCK_GROUP[0:x][0:1] = number_of_clock_group# count the number of CLOCK_GROUP that are kept in statistic, for a given level and clock state.

Latch_SEU[0:1][0:1][0:1]=0 # count the DFF Latch SEU due to direct SET on the memorizing latch for each state of input output and clock

Total_dff[0:1][0:1][0:1]=number_of_dff_programmed_in_this_state_before_radiation test # count the number of DFF in a given state of input, output and clock that are not upset by a clock SET in clock trees

Foreach(DFF)

{

If ((the DFF PosEdge Seq AuxIn Len0:2 Cen Ren0:2 Sync config remain at their initial value) then {

DFF.status = excluded_from_statistic; #upset due to or prevented by config

Total_dff[input][clkstate][output] -- ;} #removed from statistic

Else {

DFF.status = unthreaded ;}

}

Foreach(unthreaded DFF) {

If (Latch bit flip) then {

GRP_num = 0 ;

Loop = 1 ;

While(loop==1) {

If (DFF (initial input) ≠ (initial output) and all the unthreaded dff drive by the previous CLOCK_GROUP (number GRP_num+1) on clock path to the DFF, have a bit flip when (initial input) ≠ (initial output)) then {

# a more soft condition can be chosen in order to consider that some

# DFF can have extra latch bit flip

GRP_num++ ;}

Else {

loop=0 ;}

}

If (GRP_num=0) then {

Latch_SEU[input][clkstate][output]++ ;}#SEU on latch

Else{

CLOCK_GROUP_SEU[GRP_num] [clkstate]++ ;

#SET due to a CLOCK_GROUP level GRP_num

#Remove from statistic all the component derived by this clock group

Foreach(DFF drived by mtx number GRP_num in the amount on DFF clock) {

DFF = threaded ;

Total_dff[input][clkstate][output] -- ;}

For(I from 1 to M) {

Total_CLOCK_GROUP[i][clkstate] - = number_of_GROUP_level_i_drived_by_a_clock_group_number_ GRP_num ;

}

}

Else {DFF = threaded ;}

}

}

Cross_section_dff[input][clkstate][output]= Latch_SEU[input][clkstate][output] / (Total_dff[input][clkstate][output] * fluence)

Cross_section_CLOCK_GROUP[i][clkstate] = CLOCK_GROUP_SET[i][clkstate] / (Total_ CLOCK_GROUP[i][clkstate] * fluence)

Dynamic test of DFF

For this test a 24 MHz clock is provided for HIF and a variable frequency is available for PIF. In both cases, the clock is provided by the SPARTAN6 FPGA embedded on the NxBase mother board.

All structures are based on DFF that are loop on itself through an inverter. This work as a shift register with a checkerboard because at each clock pulse the data is inverted in the DFF.

Tow test are provided in order to extract the SET on asynchronous RESET and the SET on combinational logic:

Figure 12: DFF dynamic DUT

Test of configuration memory with CMIC ECC

1 CMIC by row (5 rows) is correcting the data:

• ~400 000 clock cycle checking

• 65 000 min clock cycle idle

• 24MHz clock

• After correcting 1 error of a column it restarts from first address of the same column.

• CMIC is able to fix one error in the chip

At worst case, CMIC can manage 1 error per chip per CMIC cycle (24.10⁶/465 000) = 51 error/s

CMIC ECC is stored in ST_SPREG_144x27m4:

• 132 Word for row2

• 128 Word for another row

The CMIC for one row work as follow:

• 4 signatures for each column

• 1 error in a signature can be corrected and Error flag is set, and the CMIC restart form the same column

• 2 errors in the same signature can’t be corrected but an Error flag is set, and the CMIC stop

CMIC test gives such information:

• Number of Single error

• Number of uncorrectable double error

Single-Event Latchup test

Single-Event Latchup test is performed at a temperature of 125°C. The NG-MEDIUM chip is heated by power resistors located under the chip on the PCB solder side. The current in the heating resistors is controlled via a PWM signal provided by the SPARTAN 6 FPGA located on the NxBase board. The power translation is realized through a power MOS-FET transistor located directly on the NG-MEDIUM bringup board.

Supplies are set to their max value (+10%):

• VDD1V2: 1.32V

• VDD3V3: 3.63V

• VDD2V5: 2.75V

• VDD1V8: 1.98V

Single-Event Latchup test is done up to a fluence of 10⁷p/cm^-2 with the ion providing the highest LET available: ¹²⁴Xe³⁵⁺ (LET=62.5 MeV/mg/cm²).

Prior to the irradiation, a chess board pattern (even address: 010101…, odd address: 101010…) for even column and the inverted chess board for odd column is loaded into the DUT configuration.

During the whole irradiation duration, current for every power supply rail is monitored by the NxBase board in real time in order to detect single-event latchup.

The temperature is regulated using a PID controller located on the test computer. The DUT internal temperature sensor is calibrated by an external sensor located near the heating resistors.

Results for heavy ions tests

For SEU/SET VDD1V2 Core supply = 1.08V is the supply applied at the input of the chip, since no voltage sensor was used, the real voltage in the chip was 1.045V, so that the robustness results are degraded.

Temperature: 19°C 34°C

Configuration memory at chip level

Configuration memory cross-section

Cross-section confidence intervals of 95% (α = 5%) are calculated for:

Relative fluence uncertainty of UCL is δF/F = 5%.

SEU has been tested for DUT 6 and 7 from LET = 3.3 MeV.cm²/mg to LET = 62.5 MeV.cm²/mg. Tilted radiation are tested to study angle dependency of the sensitivity of hardened structure.

The table and graphic below give the measured cross-section for the two chips under test and the Weibull fittings are given for normal incidence. DUT6 and DUT7 measurements are correlating correctly. So, the two chip data are merged for the next curves and studies.

For tilted incidence when comparing the cross-section for rotation angle phi=0° and 90°, the worst case at chip level is for 0°.

Table 8: Weibull Fit Parameters for configuration SEU cross-section

Table 9: Configuration SEU cross-section(LET) of DUT6&7

Figure 13: Configuration SEU cross-section(LET) of DUT6&7

Table 10: NG_medium Configuration SEU cross-section(LET)

Table 11: Weibull Fit Parameters for configuration SEU cross-section

Figure 14: NG_medium configuration SEU cross-section(LET)

Configuration memory with CMIC

As shows the curve below and as expected, the measured configuration cross section doesn’t change when the CMIC is activated.

CMIC stops when 2 errors occur in the same signature. No double error in a same signature is observed in the reference memory: ST_SPREG_144x27m4. The configuration double error in a same signature cross section is calculated by dividing the double error number by config number and fluence. As comparison an upper of the cross section of double error due to accumulation is deduced from the config SEU cross-section and the table and formula below with the fluxes used at UCL. At the LET of 62.5 MeV.cm²/mg the cross-section of SEU accumulation is negligible regarding to the observed double error; indeed at 62.5 MeV.cm²/mg, the double error observed are on the same bit of this two local address couple in 4*n input matrix: (2,4);(1,3) corresponding of (Wordline2 of cross_data_select4 and WL0 of cross_data_cell4) and (Wordline1 and 3 of cross_data_select4). This double error is MBU on the same signature because local addresses are physically ordered 0, 1, 3, 2, 4.

At a LET of 32.4 MeV.cm²/mg only 1 MBU is record among the 4 double errors, the other double errors are cumulative effect.

At a LET of 20.4 MeV.cm²/mg even if the CMIC report a double error, no error can be read in the configuration memory

Figure 15: CMIC data

In any application, the scrubbing failure cross section is below or equal to the config double error (=scrubbing failure) cross-section measured at UCL. At a LET of 62.5 MeV.cm²/mg the failure cross-section is more than one decade below the SEU cross-section

But when single error occur the scrubbing needs some time to correct it, so that the error remains during this time; then a flag is set, so the user has to verify if it is required to reset the application.

Figure 16: SEU config cross-section(LET) with CMIC

Table 12: SEU config cross-section(LET) with CMIC

DPRAM

The cross-section of single corrected error is plotted on the curve below. The EDAC is always able to correct the single error when the data is read. So, the error cross-section with EDAC is lowered at the level of the double error cross section on the curve below. DPRAM cross-section is two orders of magnitude lower than those of the config memory and the bit occurrence of 2 752 512 is lower than those of configuration bit, meaning that the DPRAM contribution to chip SER is negligible.

Table 13: SEU DPRAM cross-section(LET)

Figure 17: SEU DPRAM cross-section(LET)

Static DFF SEU, Static Clock SET

As show the data and the curve below the DFF cross-section is below the cross-section of the configuration memory. The SET number is considered to be the output number of a matrix system to which propagate a clock a SET that make flip more than two driven DFF. The SET cross section per system matrix is bigger than the one of configuration memory but the occurrence of mtx_sys in the test design is 1008. So the cross-section is calculated in cm² per config memory, the cross-section is negligible compared to the config cross-section, meaning that the contribution to chip SER is negligible compared to the one of config.

Table 14: DFF SEU and Clock SET cross-section(LET)

Figure 18: DFF SEU and Clock SET cross-section(LET)

Toggle DFF error

The curve below gives the cross section of dff context error, the error cause by:

-DFF SEU

-Config SEU in DFF, LUT or MATRIX

-Clock SET

-Combinational logic SET

The curve below shows the dff context error cross section per dff and per config, the cross section per config is below the configuration cross section, meaning that for toggle dff application clocked at 24MHz the chip SER contribution is below than the one of configuration memory.

At a LET of 62.5 MeV.cm²/mg, the static error cross section deduced from static dff is correlated with the toggle dff error cross section. Thus at 62.5 MeV.cm²/mg the toggle dff error are dominated by clock SET.

Table 15: Toggle dff error cross-section(LET)

Figure 19: Toggle dff error cross-section(LET)

SEFI

SEFI were recorded, a SEFI in the FPGA control part mean that the reading or writing of the configuration/context is not possible, while the application status is unknown. The SEFI cross-section contribution to chip cross-section is negligible compared to the one of config.

Table 16 : SEFI cross-section(LET)

Figure 20: SEFI cross-section(LET)

Single-Event Latchup test

For the Single-Event Latchup test, all power supply voltages are set at their maximum (+10%). Silicon chip temperature is set to 125°C and is regulated by a PID controller implemented in the test software.

This test is performed with the ion providing the highest LET available: ¹²⁴Xe³⁵⁺ (LET=62.5 MeV/mg/cm²) up to a fluence of 10⁷p/cm^-2.

The same NxBase mother (#04) was used to perform all tests.

The test was performed on the following DUT:

• #1718_004 equipped on bringup board #06

• #1718_052 equipped on bringup board #11

• #1808_004 equipped on bringup board #14

No single latchup event was detected during any of the test periods for any DUT.

Results for protons tests

For SEU/SET VDD1V2 Core supply = 1.08V is the supply applied at the input of the chip, since no voltage sensor was used, the real voltage in the chip was 1.045V, so that the robustness results are degraded.

Configuration memory at chip level

Configuration memory cross-section

Cross-section confidence intervals of 95% (α = 5%) are calculated for:

Relative fluence uncertainty of PSI is δF/F = 5%.

SEU has been tested for DUT #53 and DUT #52 from Energy = 30 MeV to Energy = 230 MeV. Tilted variations are not relevant for proton tests.

The table and graphic below give the measured cross-section for the two chips under test and the Weibull fittings. Since DUT #53 and DUT #52 measurements are correlating correctly, the two chips data are merged for the next curves and studies.

Table 17: Configuration SEU cross-section(energy) of DUT #53 and DUT #52

Table 18: Weibull Fit Parameters for configuration SEU cross-section

Figure 21: Configuration SEU cross-section(Energy) of DUT #53 and DUT #52

Table 19: Configuration SEU cross-section(energy) for merged DUT #53 + DUT #52

Table 20: Weibull Fit Parameters for configuration SEU cross-section (for merged DUT #53 and DUT #52)

Figure 22: Configuration SEU cross-section(Energy) of merged DUT #53 + DUT #52

Configuration memory with CMIC

As shows the table below and as expected, the number of corrected configuration memory errors is similar to results showed by the non-CMIC test.

CMIC stops when 2 errors occur in the same signature. No double error in a same signature is observed in the reference memory (ST_SPREG_144x27m4). The configuration double error in a same signature cross section is calculated by dividing the double error number by config number and fluence.

Table 21: SEU config cross-section(energy) with CMIC for single error

Table 22: SEU config cross-section(energy) with CMIC for double error

Figure 23: Configuration SEU cross-section(Energy) of DUT #52 with CMIC

Figure 24: Configuration SEU cross-section(Energy) of DUT #53 with CMIC

DPRAM

The cross-section of single corrected error is plotted on the curve below. The EDAC is always able to correct single errors when the data is read. So, For this test, the clock frequency used by the design is 10MHz.

Table 23: single SEU DPRAM cross-section (energy)

Table 24: double SEU DPRAM cross-section (energy)

Figure 25: SEU DPRAM cross-section(Energy) of DUT #53 and DUT #52

Static DFF SEU, Static Clock SET

As show the data and the curve below the DFF cross-section is similar to the cross-section of the configuration memory.

The SET number is considered to be the output number of a matrix system to which propagate a clock a SET that make flip more than two driven DFF. No SET where detected during the test.

Table 25: DFF SEU and Clock SET cross-section(Energy)

Figure 26: DFF SEU cross-section(Energy) of DUT #53 and DUT #52

Toggle DFF error

The curve below gives the cross section of dff context error, the error might be caused by:

-DFF SEU

-Config SEU in DFF, LUT or MATRIX

-Clock SET

-Combinational logic SET

The curve below shows the dff context error cross section per dff and per config. The cross section per config is below the configuration cross section, meaning that for toggle dff application the chip SER contribution is below than the one of configuration memory.

Table 26: Toggle dff error cross-section(energy)

Figure 27: Toggle DFF cross-section(Energy) of DUT #53 and DUT #52 @60MHz

The curve below shows the dff context error cross section per dff relative to the fabric clock frequency, we can see little to no effect for the tested frequencies (10MHz, 35MHz, 60MHz). The test vehicle was not designed to support higher fabric frequencies.

Table 27: Toggle dff error cross-section(fabric frequency) energy=230MeV

Figure 28: DFF SEU cross-section(Frequency) of DUT #53 and DUT #52 at 230MeV

SEFI

SEFI were recorded. A SEFI in the FPGA control part mean that the reading or writing of the configuration/context is not possible, while the application status is unknown. The SEFI cross-section contribution to chip cross-section is negligible compared to the one of config.

Table 28 : SEFI cross-section(energy)