Revision | Date | Originator | Comments |
1.0 | 04/02/2019 | D. CHAMEREAU | |
1.1 | 01/16/2020 | D. CHAMEREAU | Correcting the configuration setup table. Adding pin 1 on jumpers on Top assembly Drawing + level for switches. |
1.2 | 01/30/2020 | D. CHAMEREAU | Converting the pin mapping between NG-LARGE pin names and connectors/Signal Name for Nxmap. |
Table of Contents
Introduction
Scope of the Document
This document describes how to use the board “NG-LARGE Dev. Kit V1.0” with the different interfaces.
Functional description
Board Top assembly drawing
Installation procedure
Foreword:
If the NG-LARGE dev. Kit is provided with a FPGA socket, please to ensure the wires of socket fan is plugged on the connector J45 for cooling the NG-LARGE.
AC/DC power adapter 12V/5A is needed to plug on the J44 jack connector.
DDR memory setup:
In case of DDR2 SO-DIMM module plugged, set the jumper J47 in
position 1-2.
In case of DDR3 SO-DIMM module plugged, set the jumper J47 in
position 2-3.
Configuration setup: refer to chapter 3.
Press the Power-button SW18 to power-on the NG-large DevKit.
Notes :
a soft reset (Bitstream reset) is active by pressing the SW19 button.
a Hard reset is active by pressing the SW17 button.
Power leds
On board power Leds | Comments |
D15 | ON if 3V3 is good |
D21 | ON if 12V is good |
D16 | ON if 2V5 is good |
D17 | ON if 1V2_Core is good |
D18 | ON if HSSL_1V2_Core is good |
D19 | ON if DDR voltage is good |
Configuration setup
First, please to choose the targeted configuration mode by the external MODE jumpers:
Config. mode | J41 = MOD2 | J43 = MOD1 | J42 = MOD0 | Comments |
Mode 0: Master SPI | Pos. 2-3 | Pos. 2-3 | Pos. 2-3 | The SPI flash board must be plugged on J29 connector |
Mode 1: Master SPI +SPI Power Supply | Pos. 2-3 | Pos. 2-3 | Pos. 1-2 | The SPI flash board must be plugged on J29 connector |
Mode 2: Slave Space Wire | Pos. 2-3 | Pos. 1-2 | Pos. 2-3 | J17 is the configuration mode connector by the spacewire interface. |
Mode 3: Reserved (Jtag only) | Pos. 2-3 | Pos. 1-2 | Pos. 1-2 | |
Mode 4 : Slave 8 bits parallel | Pos. 1-2 | Pos. 2-3 | Pos. 2-3 | |
Mode 5 : Slave 16 bits parallel | Pos. 1-2 | Pos. 2-3 | Pos. 1-2 | |
Mode 6 : Reserved | Pos. 1-2 | Pos. 1-2 | Pos. 2-3 | |
Mode 7: Test Mode | Pos. 1-2 | Pos. 1-2 | Pos. 1-2 |
An optional slave 8 bits parallel mode is possible via an other Dev Kit and via the connector J40, configuring the jumpers J25 and J28. Please to join the support for more informations.
Dev Kit parallel Configuration mode: | Jumper J25 | Jumper J28 |
Master Dev. Kit | Position 1-2 | removed |
// Slave Dev. Kit | Position 2-3 | Set |
Other Jumpers to configure by default:
J28, J38 must be removed.
Set J25 in position 1-2.
External identification pins can be configured by the following jumpers:
Ident. pins | Corresponding jumpers: |
ID0 | =0 if J23 set/ = 1 if removed |
ID1 | =0 if J26 set/ = 1 if removed |
ID2 | =0 if J24 set/ = 1 if removed |
ID3 | =0 if J27 set/ = 1 if removed |
Configuration clock mode:
The configuration clock frequency range is 0 to 100 MHz max +/- 10%.
Config. Clock source | Jumpers setup |
Internal 100MHz +/-% | Set J18/ remove J19 and J20 |
On board 25 MHz 50ppm | Set J20/ remove J19 and J18 |
External via SMA (J21) | Set J19/ remove J18 and J20 |
Configuration Leds:
Leds | designator | Function |
“Ready” | D12 | Configuration done without errors |
“Error” | D13 | Configuration error |
“Trigger” | D14 | Configuration done with 1st errors |
JTAG interfaces
JTAG for FPGA configuration
The NG-LARGE JTAG can be used either by the ANGIE module via the J22 connector or by an external Host or 2nd Dev Kit via the J35 connector.
Important note: the JTAG clock must be < ½ * configuration clock !!!
NG-LARGE pins | J35 connector pins |
TCK | 4 |
TMS | 2 |
TDI | 8 |
TDO | 6 |
TRST | 10 |
The configuration voltage is 3.3V
To use this interface on J35, you must set a jumper on J36 at position 2-3
And not use the J22 connector.
Other JTAG interfaces
The 20 pins HE10 connector J3 offer a standard JTAG interface as below:
Signal name NG-LARGE pins | J3 connector pins |
IO_B12D03N ARM_DBGRQ IO_B12D03P ARM_RST IO_B12D05N ARM_DBGACK IO_B12D05P ARM_TRSTn IO_B12D06N ARM_RTCK IO_B12D06P ARM_TMS IO_B12D07N ARM_TCK IO_B12D07P ARM_TDO IO_B12D08N ARM_TDI | 17 15 19 3 11 7 9 13 5 |
The bank n°12 voltage is 3.3V
This JTAG interface is compliant with Lauterbach JTAG connector for ARM target .on The internal ARM-R5 processor can be debugged by a JTAG HE10-20pts connector (J3) and can use an external 64K word SRAM (IS61WV6416DBLL-10T) and Dual-UART to USB interfaces (connector J6). For this, connect the dedicated ARM-R5 pins to the eFPGA IOs as below.
DDR2/3 interface
The DDR2/DDR3 interface is routed to the standard 204 pins SO-DIMM connector (J12) in 32 bits wide version.
The max. frequency must be 400 MHz or 800Mbits/s.
Before powering the Dev. Kit.
In case of DDR2 SO-DIMM module plugged, set the jumper J47 in position 1-2.=> All voltage banks to 1.8V.
In case of DDR3 SO-DIMM module plugged, set the jumper J47 in position 2-3. => All voltage banks to 1.5V.
Refer to the schematic to drive all the signals.
NG-LARGE Signal Name Pin name | NG-LARGE Signal Name Pin name |
IO_B08D01N_DQ_SWDO DDR_DQ4 IO_B08D01P_DQ_SWDO DDR_DQ0 IO_B08D02N_DQ_SWSO DDR_DM0 IO_B08D02P_DQ_SWSO DDR_DQ1 IO_B08D03N_DQS_SWDI DDR_DQS0_N IO_B08D03P_DQS_SWDI DDR_DQS0_P IO_B08D04N_DQ_SWSI DDR_DQ5 IO_B08D04P_DQ_SWSI DDR_DQ6 IO_B08D05N_DQ DDR_DQ2 IO_B08D05P_DQ DDR_DQ3 IO_B08D06N_CAL DDR_RSTn IO_B08D06P_DQ DDR_DQ7 IO_B08D07N DDR_A3 IO_B08D07P DDR_CS/ IO_B08D08N DDR_A2 IO_B08D08P DDR_A6 IO_B08D09N DDR_A15 IO_B08D09P DDR_A14 IO_B08D10N DDR_A4 IO_B08D10P DDR_A11 IO_B08D11N DDR_BA1 IO_B08D11P DDR_CKE IO_B08D12N_DQ DDR_DQ8 IO_B08D12P DDR_A7 IO_B08D13N_DQ DDR_DQ12 IO_B08D13P_DQ DDR_DQ9 IO_B08D14N_DQ_SWDO DDR_DQ10 IO_B08D14P_DQ_SWDO DDR_DQ13 IO_B08D15N_DQS_SWSO DDR_DQS1_N IO_B08D15P_DQS_SWSO DDR_DQS1_P IO_B08D16N_DQ_SWDI DDR_DQ14 IO_B08D16P_DQ_SWDI DDR_DQ11 IO_B08D17N_DQ_SWSI DDR_DM1 IO_B08D17P_DQ_SWSI DDR_DQ15 IO_B09D01N_DQ_SWDO DDR_DQ31 IO_B09D01P_DQ_SWDO DDR_DQ27 IO_B09D02N_DQ_SWSO DDR_DM3 IO_B09D02P_DQ_SWSO DDR_DQ26 IO_B09D03N_DQS_SWDI DDR_DQS3_N IO_B09D03P_DQS_SWDI DDR_DQS3_P IO_B09D04N_DQ_SWSI DDR_DQ29 IO_B09D04P_DQ_SWSI DDR_DQ30 IO_B09D05N_DQ DDR_DQ25 IO_B09D05P_DQ DDR_DQ24 IO_B09D06N_CAL DDR_ODT IO_B09D06P_DQ DDR_DQ28 IO_B09D07N DDR_A10 IO_B09D07P DDR_BA0 IO_B09D08N DDR_A5 IO_B09D08P DDR_A9 IO_B09D09N DDR_BA2 IO_B09D09P DDR_A12 IO_B09D10N DDR_A8 IO_B09D10P DDR_A1 IO_B09D11N DDR_CLK_N IO_B09D11P DDR_CLK_P IO_B09D12N_DQ DDR_DM2 IO_B09D12P DDR_A0 IO_B09D13N_DQ DDR_DQ23 IO_B09D13P_DQ DDR_DQ22 IO_B09D14N_DQ_SWDO DDR_DQ21 IO_B09D14P_DQ_SWDO DDR_DQ20 IO_B09D15N_DQS_SWSO DDR_DQS2_N IO_B09D15P_DQS_SWSO DDR_DQS2_P IO_B09D16N_DQ_SWDI DDR_DQ19 IO_B09D16P_DQ_SWDI DDR_DQ18 IO_B09D17N_DQ_SWSI DDR_DQ17 IO_B09D17P_DQ_SWSI DDR_DQ16 | IO_B10D07N DDR_CAS/ IO_B10D07P DDR_A13 IO_B10D08N DDR_RAS/ IO_B10D08P DDR_WE/ |
CLOCKs
Global clock
The half top of the NG-Large will be supplied by a 25 MHz/ 50ppm oscillator named “OSC_TOP” and/or a user clock named “OSC_BY_Socket” (please to insert it on the socket U8 (needed 2*5mm SMD/2.5V oscillator).
The half bottom of the NG-Large will be supplied by a 25 MHz/ 50ppm on socket oscillator or/and an external oscillator on SMA connector. In case of external source, please to respect the frequency range of 20 to 50 MHz or 40 to 100 MHz according to bitstream programmed.
Clock Sources | Supplying NG-LARGE Area | Signals | NG-large Pins | Bank Voltage |
25 MHz | Half-Top | OSC_BY_Socket | IO_B00D01P_CLK | 2.5V |
25 MHz | Half-Top | OSC_TOP | IO_B18D02P_CLK | 3.3V |
25 MHz | Half-Bottom | OSC_BOTTOM | IO_B11D11P_CLK | 3.3V |
Adjustable | Half-Bottom | SMA_CLK_IN | IO_B11D12P_CLK | 3.3V |
HSSL/SERDES reference clock
For convenient reasons , only 2 HSSL high speed blocks (on 4) are used on the Dev Kit and the reference clocks are shared as described on this table:
HSSL | Sources | Signals | NG-large Pins |
HSSL 2 | 2 possible sources are configured by the J53 jumper position: 1-2: 156.25 MHz / 20ppm oscillator 2-3: external LVCMOS oscillator on SMA connector J48. | HSSL2_CLKREF_P | HSSL2_CLKREFP |
HSSL2_CLKREF_N | HSSL2_CLKREFN | ||
HSSL3 | External by the FMC N°2 connector J2 (on pins G6,G7) | Dev_CLKREF_P | HSSL3_CLKREFP |
Dev_CLKREF_N | HSSL3_CLKREFN |
All Clock references are in LVDS voltage.
Both supports a frequency range from 100 to 200 MHz max.
Others interfaces
Dual-UART to USB interfaces
A dual UART to USB interface is connected to the eFPGA or used by the ARM-R5 after mapping through the e-FPGA.
The bank 15 voltage is 3.3V.
Signal name NG-LARGE pins |
IO_B15D01P Uart_TXD1 IO_B15D01N Uart_RXD1 IO_B15D02N Uart_CTS1 IO_B15D02P Uart_RTS1 IO_B15D03P Uart_TXD2 IO_B15D03N Uart_RXD2 IO_B15D04N Uart_CTS2 IO_B15D04P Uart_RTS2 IO_B15D05P TC_485 |
External SRAM
Bank 15,16,17 used with 3.3V Voltage.
Signal name NG-LARGE pins |
IO_B16D08P Sram_A0 IO_B17D03P Sram_A1 IO_B16D07P Sram_A10 IO_B16D07N Sram_A11 IO_B16D06P Sram_A12 IO_B16D06N Sram_A13 IO_B16D03P Sram_A14 IO_B16D05N Sram_A15 IO_B17D03N Sram_A2 IO_B17D08N Sram_A3 IO_B17D07N Sram_A4 IO_B17D05P Sram_A5 IO_B17D11N Sram_A6 IO_B16D09N Sram_A7 IO_B16D05P Sram_A8 IO_B16D08N Sram_A9 IO_B16D10P Sram_CE/ IO_B16D01P Sram_D0 IO_B16D01N Sram_D1 IO_B17D06N Sram_D10 IO_B17D06P Sram_D11 IO_B17D04P Sram_D12 IO_B17D05N Sram_D13 IO_B17D02P Sram_D14 IO_B17D02N Sram_D15 IO_B16D02P Sram_D2 IO_B16D03N Sram_D3 IO_B16D02N Sram_D4 IO_B16D04P Sram_D5 IO_B16D04N Sram_D6 IO_B17D01P Sram_D7 IO_B17D07P Sram_D8 IO_B17D01N Sram_D9 IO_B17D10N Sram_LB/ IO_B17D08P Sram_OE/ IO_B17D10P Sram_UB/ IO_B16D10N Sram_WE/ |
SpaceWire interfaces
The dev. Kit provide 4 user spacewires interfaces arranged like below:
All SpaceWire signals are in LVDS voltage.
2 standard Spacewire connectors J7 and J8.
SpaceWire connectors | Signals | NG-large Pins |
J7: Spacewire N°1 | SW1_Dout_P | IO_B06D14P_DQ_SWDO |
SW1_Dout_N | IO_B06D14N_DQ_SWDO | |
SW1_Sout_P | IO_B06D15P_DQS_SWSO | |
SW1_Sout_N | IO_B06D15N_DQS_SWSO | |
SW1_Din_P | IO_B06D16P_DQ_SWDI | |
SW1_Din_N | IO_B06D16N_DQ_SWDI | |
SW1_Sin_P | IO_B06D17P_DQ_SWSI | |
SW1_Sin_N | IO_B06D17N_DQ_SWSI | |
J8: Spacewire N°2 | SW2_Dout_P | IO_B06D01P_DQ_SWDO |
SW2_Dout_N | IO_B06D01N_DQ_SWDO | |
SW2_Sout_P | IO_B06D02P_DQ_SWSO | |
SW2_Sout_N | IO_B06D02N_DQ_SWSO | |
SW2_Din_P | IO_B06D03P_DQS_SWDI | |
SW2_Din_N | IO_B06D03N_DQS_SWDI | |
SW2_Sin_P | IO_B06D04P_DQ_SWSI | |
SW2_Sin_N | IO_B06D04N_DQ_SWSI |
2 optional Spacewire interfaces through FMC N°1 connector (J1) using the FMC StarFibre/Starwire expansion board (Star-dundee) .
This FMC board must be configured with 2 spaceWires on 4 activated :
SpW1 and SpW4 only by the following switches on expansion board !
Dip SW1 = 00000001
Dip SW2 = 10110000
SpaceWire connectors | Signals | NG-large Pins |
SpW1 interface | SW1_Dout_P | IO_B20D14P_DQ_SWDO |
SW1_Dout_N | IO_B20D14N_DQ_SWDO | |
SW1_Sout_P | IO_B20D15P_DQS_SWSO | |
SW1_Sout_N | IO_B20D15N_DQS_SWSO | |
SW1_Din_P (= SpW_B1) | IO_B19D16P_DQ_SWDI | |
SW1_Din_N (= SpW_B1) | IO_B19D16N_DQ_SWDI | |
SW1_Sin_P (= SpW_B2) | IO_B19D17P_DQ_SWSI | |
SW1_Sin_N (= SpW_B2) | IO_B19D17N_DQ_SWSI | |
SpW4 interface | SW4_Dout_P | IO_B19D14P_DQ_SWDO |
SW4_Dout_N | IO_B19D14N_DQ_SWDO | |
SW4_Sout_P | IO_B19D15P_DQS_SWSO | |
SW4_Sout_N | IO_B19D15N_DQS_SWSO | |
SW2_Din_P (= SpW_A2) | IO_B20D16N_DQ_SWDI | |
SW2_Din_N (= SpW_A2) | IO_B20D16P_DQ_SWDI | |
SW2_Sin_P (= SpW_A4) | IO_B20D17P_DQ_SWSI | |
SW2_Sin_N (= SpW_A4) | IO_B20D17N_DQ_SWSI |
SERDES links
For single tests, 1 Gbits Raw SERDES transceiver is available on HSSL2 block as below:
NG-LARGE Pins | Signal name | SMA Connectors |
HSSL2_TX6P | HSSL2_TX6_P | J49 |
HSSL2_TX6N | HSSL2_TX6_N | J50 |
HSSL2_RX6P | HSSL2_RX6_P | J51 |
HSSL2_RX6N | HSSL2_RX6_N | J52 |
Note that on board, these signals are AC-coupled.
Other SERDES links are available to drive many FMC daughter board on both FMC N°1 and N°2 connectors. See chapter 3.
Please to refer on the NG-LARGE electrical specification for compliant voltage levels.
GPIOs interfaces
Switches,Push button, Leds
8 Push button,8 switches and 8 user leds are available on board.
Bank Voltage: 3.3V
Green Leds (Active to 0) | NG-Large Pins | Bank | Switches Right Position : 0V Left Position : 3.3V | NG-Large Pins | Bank |
D1 D2 D3 D4 D5 D6 D7 D8 | IO_B11D05N IO_B11D05P IO_B11D06N IO_B11D06P IO_B11D07N IO_B11D07P IO_B11D08N IO_B11D08P | 11 | SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 | IO_B12D12P IO_B12D12N IO_B12D11P IO_B12D11N IO_B12D10P IO_B12D10N IO_B12D09P IO_B12D09N | 12 |
Push buttons (pressed = 0V) | NG-Large Pins | Bank | |||
PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 | IO_B11D01N IO_B11D01P IO_B11D02N IO_B11D02P IO_B11D03N IO_B11D03P IO_B11D04N IO_B11D04P | 11 |
GPIOs connectors
J15 and J16 HE10 connectors contains 38 user GPIOs which are connected to bank 13 and 14 with Bank Voltage to 3.3V.
J15 Pins | NG-Large Pins | Bank | J15 Pins | NG-Large Pins | Bank |
1 3 5 7 9 11 13 15 17 19 | IO_B14D12P IO_B14D12N IO_B14D11P IO_B14D11N IO_B14D10P IO_B14D10N IO_B14D09P IO_B14D09N IO_B14D08P IO_B14D08N | 14 | 2 4 6 8 10 12 14 16 18 | IO_B14D07P IO_B14D07N IO_B14D06P IO_B14D06N IO_B14D05P IO_B14D05N IO_B14D04P IO_B14D04N IO_B14D03P | 14 |
J16 Pins | NG-Large Pins | Bank | J16 Pins | NG-Large Pins | Bank |
1 3 5 7 9 11 13 15 17 19 | IO_B14D03N IO_B13D01N IO_B13D01P IO_B13D02N IO_B13D02P IO_B13D03N IO_B13D03P IO_B13D04N IO_B13D04P IO_B13D05N | 14 15 … | 2 4 6 8 10 12 14 16 18 | IO_B13D10N IO_B13D06N IO_B13D06P IO_B13D07N IO_B13D07P IO_B13D08N IO_B13D08P IO_B13D09N IO_B13D09P | 15 |
Please to refer to the schematic.
Optional FMC boards
On FMC connector N°1 (J1 on Dev.Kit)
For convenient reasons and to manage all the below FMC boards not compliant each other, only some channels or functions are connected to the development kit.
Here is the summary of FMC functionalities:
EV12AD550 (e2v)FMC with ESISTREAM digital links: only ADC channel A used (/2)
StarFibre/StarWire FMC expansion board : 2 STARFIBRE + 2 StarWire interfaces (W1 and W4).
Quad Gethernet FMC P0481 : only Ethernet Port 0 (/4)
XM105 FMC debug board (Xilinx) : mainly MICTOR interface (+ some signals routed)
FMC N°1 daughter boards | J13 connector | Comments |
EV12AD550 (e2v) | Set position 1-2 | In case of EV12AD550 FMC Mezzanine Board: Set G9 in position 1-2 Set Vcc_Adj= 2.5V Set JP7 in position 1-2 or VCCIOH = 2.5V Set JP6 in position 1-2 or VCCD= 2.5 SPI_mode=0 (FPGA SPI master) / = 1 (STM32 SPI master) |
StarFibre/StarWire expansion board (Star-dundee) | Set position 1-2 | Only 2 spaceWires link have been routed on 4: SpW1 and SpW4. Set the corresponding DIP switches as below: Dip SW1 = 00000001 Dip SW2 = 10110000 |
Quad GigaEthernet FMC P0481 (TERASIC) | Set position 1-2 | Only the ethernet Port 0 is routed through the P0481 must be configured in GMII mode only. Set SW0 in mode : 1-ON, 4-ON |
XM105 debug board (Xilinx) | Set position 1-2 | Only the mictor and some signals are routed to the FPGA. See the Dev . Kit. Schematic. |
Custom FMC board (TBD) | Set position 1-2 if GPIO in 2.5V used or 2-3 if 3.3V used | Please to refer to schematic to see the available routed signals |
The mapping with the NG-LARGE is indicated in the document “MFC_mapping.xlsx”
Besides, 15 additional GPIOS signals have been added “F1_IO(0 to 15)”. Refer to the NG-LARGE dev Kit schematic.
EV12AD500A Setup
As custom EV12AD500A ADC daughter board would request time to develop, it is more convenient to use the available expansion board EV12AD5x0-EK ( by e2v) .
To be plugged on used on FMC connector N°1:
For practical reason, Only the ADC channel A would be used / mapped below
NG-LARGE Carrier Dev Kit Signals | Dir. | FMC Std signals | EV12AD500A pins | |
Gbits transceivers |
| DP0_M2C_P/_N | ASL1p/n ( CML logic) | |
Gbits transceivers |
| DP1_M2C_P/_N | ASL3p/n ( CML logic) | |
Gbits transceivers |
| DP2_M2C_P/_N | ASL2p/n ( CML logic) | |
Gbits transceivers |
| DP3_M2C_P/_N | ASL0p/n ( CML logic) | |
SYNC_P /n (LVDS) | HB17_p /n | SYNCTRIG_P /N (LVDS) | ||
SYNCO (LVDS) |
| CLK1_M2C_P /N | SYNCOP/N (LVDS) | |
SSO (LVDS) |
| GBTCLK0_M2C_P | SSOp/n (LVDS) | |
SPI_mode |
| HA18_N | SPI bus shared control | |
Reset DUT | HA19_P | reset | ||
SCLK (2.5V) | HA19_N | SCLK | ||
Cs (2.5V) | HA20_P | csn | ||
Mosi (2.5V) | HA20_N | mosi | ||
Miso (2.5V) | HB03_P | miso | ||
Channel A data ready | HB06_P/N | P/N_ADR | ||
Channel A control Bits 2 | HB04_P/N | P/N_AFU2 | ||
Channel A control Bits 1 | HA12_P/N | P/N_AFU1 |
Board requirements:
-12VDC/5A to plug on J23 jack connector. ( So, the NG-LARGE eval kit don’t bring power on this EV12AD5x0-EK).
- Power On/off by SW1 switch.
- The VCCIOHxx supplies must be grounded by JP7,JP9 in position “EXT” and J11,J15 connected at Gnd.
-Set the Switch S6 in position “FPGA”.
-Set the Switch S10 in position “ADC”.
- Set the SPI mode switch S4 in position “FPGA”.
- Adjust R40 potentiometer to have VCC_Adj= 2.5V. (PT18)
- Set the buffer voltage with switch G9 in “VC709-ADJ” position ( prog. At 3.3V TBC on FPGA) and not P1V8.
Software requirements:
The output of the ADC can be configured either as a LVDS DEMUX 1:1 or serial interface using the ESIstream protocol through the SPI register OUT_SEL at address 0x68:
Setting it to “1” configures the output in serial interface.
Setup ( Ref. EV12AD5x0‐EK VITA 57 FMC DUAL 12b ADC Evaluation kit)
FMC CONNECTOR N°1 (J1) MAPPING
NG-large | FMC std pins | Dual 12 bits ADC | FMC-SpW-SpFi |
HSSL2_TX2P | DP0_C2M_P |
| SpFi1_Tx_P (CML) |
HSSL2_TX2N | DP0_C2M_N |
| SpFi1_Tx_N (CML) |
HSSL2_TX1P | DP1_C2M_P |
| SpFi2_Tx_P (CML) |
HSSL2_TX1N | DP1_C2M_N |
| SpFi2_Tx_N (CML) |
HSSL2_TX4P | DP2_C2M_P |
|
|
HSSL2_TX4N | DP2_C2M_N |
|
|
HSSL2_TX3P | DP3_C2M_P |
|
|
HSSL2_TX3N | DP3_C2M_N |
|
|
HSSL2_TX5P | DP4_C2M_P |
|
|
HSSL2_TX5N | DP4_C2M_N |
|
|
HSSL2_RX2P | DP0_M2C_P | ASL1p ( CML logic) | SpFi1_Rx (CML) |
HSSL2_RX2N | DP0_M2C_N | ASL1n ( CML logic) | SpFi1_Rx (CML) |
HSSL2_RX1P | DP1_M2C_P | ASL3_p ( CML logic) | SpFi2_Rx (CML) |
HSSL2_RX1N | DP1_M2C_N | ASL3_n ( CML logic) | SpFi2_Rx (CML) |
HSSL2_RX3P | DP2_M2C_P | ASL2p ( CML logic) |
|
HSSL2_RX3N | DP2_M2C_N | ASL2_n ( CML logic) |
|
HSSL2_RX4P | DP3_M2C_P | ASL0_p ( CML logic) |
|
HSSL2_RX4N | DP3_M2C_N | ASL0_n ( CML logic) |
|
NG-LARGE pins Signal name |
IO_B19D17N_DQ_SWSI Esi_ADR_SWB2_N IO_B19D17P_DQ_SWSI Esi_ADR_SWB2_P IO_B20D04N_DQ_SWSI Esi_AFU1_N IO_B20D04P_DQ_SWSI Esi_AFU1_P IO_B19D13N_DQ Esi_AFU2_N IO_B19D13P_DQ Esi_AFU2_P IO_B19D03N_DQS_SWDI Esi_CSn IO_B19D06P_DQ Esi_MISO IO_B19D07P Esi_MOSI IO_B20D09P Esi_Reset IO_B19D09N Esi_SCLK IO_B20D12N_DQ Esi_SPImode IO_B20D06N_CAL Esi_SSO_SF_RCLK0_N IO_B20D06P_DQ Esi_SSO_SF_RCLK0_P IO_B20D05N_DQ Esi_SYNCO_N IO_B20D05P_DQ Esi_SYNCO_P IO_B19D12N_DQ Esi_SYNCTRIG_N IO_B19D12P Esi_SYNCTRIG_P GEthernet interface IO_B19D01N_DQ_SWDO NET0_GTXCLK IO_B23D06N_CAL NET0_INTn IO_B20D13N_DQ NET0_MDC IO_B20D13P_DQ NET0_MDIO IO_B23D15P_DQS_SWSO NET0_RSTn IO_B19D10P_CLK NET0_RX_CLK IO_B19D10N NET0_RX_CRS IO_B20D10N NET0_RX_D0 IO_B20D09N NET0_RX_D1 IO_B20D11P NET0_RX_D2 IO_B20D10P NET0_RX_D3 IO_B20D07N NET0_RX_D4 IO_B20D11N NET0_RX_D5 IO_B20D08N NET0_RX_D6 IO_B20D07P NET0_RX_D7 IO_B20D12P NET0_RX_DV IO_B23D17N_DQ_SWSI NET0_RXS_COL IO_B19D09P_CLK NET0_TX_CLK IO_B19D08P NET0_TX_D0 IO_B19D08N NET0_TX_D1 IO_B19D07N NET0_TX_D2 IO_B19D05N_DQ NET0_TX_D3 IO_B19D06N_CAL NET0_TX_D5 IO_B19D05P_DQ NET0_TX_D7 IO_B19D01P_DQ_SWDO NET0_TX_EN IO_B19D02P_DQ_SWSO NET0_TX_ER IO_B19D02N_DQ_SWSO LED_DS1 IO_B19D03P_DQS_SWDI LED_DS2 IO_B19D04N_DQ_SWSI LED_DS3 IO_B19D04P_DQ_SWSI LED_DS4 IO_B23D10P_CLK TRACE_CLK IO_B23D07N TRACEPKT12 IO_B23D08N TRACEPKT13 IO_B20D03N_DQS_SWDI TRACEPKT7 |
IO_B20D16N_DQ_SWDI SpW_A2_N IO_B20D16P_DQ_SWDI SpW_A2_P IO_B20D17N_DQ_SWSI SpW_A4_N IO_B20D17P_DQ_SWSI SpW_A4_P IO_B19D16N_DQ_SWDI SpW_B1_N IO_B19D16P_DQ_SWDI SpW_B1_P IO_B20D14N_DQ_SWDO SpW1_Dout_N IO_B20D14P_DQ_SWDO SpW1_Dout_P IO_B20D15N_DQS_SWSO SpW1_Sout_N IO_B20D15P_DQS_SWSO SpW1_Sout_P IO_B19D14N_DQ_SWDO SpW4_Dout_N IO_B19D14P_DQ_SWDO SpW4_Dout_P IO_B19D15N_DQS_SWSO SpW4_Sout_N IO_B19D15P_DQS_SWSO SpW4_Sout_P IO_B23D04P_DQ_SWSI F1_GA0 IO_B23D06P_DQ F1_GA1 IO_B23D08P F1_IO0 IO_B23D11P F1_IO1 IO_B23D10N F1_IO10 IO_B23D11N F1_IO11 IO_B23D16N_DQ_SWDI F1_IO12 IO_B23D12N_DQ F1_IO13 IO_B23D12P F1_IO14 IO_B23D16P_DQ_SWDI F1_IO15 IO_B23D15N_DQS_SWSO F1_IO2 IO_B23D17P_DQ_SWSI F1_IO3 IO_B23D14P_DQ_SWDO F1_IO4 IO_B23D14N_DQ_SWDO F1_IO5 IO_B23D13N_DQ F1_IO6 IO_B23D13P_DQ F1_IO7 IO_B23D09N F1_IO8 IO_B23D09P_CLK F1_IO9 IO_B01D04P F1_TCK IO_B01D05N F1_TDI IO_B01D05P F1_TDO IO_B01D06N F1_TMS |
On FMC connector N°2 (J2 on Dev.Kit)
For convenient reasons, only 2 FMC evaluations boards are managed on the FMC connector N°2:
DAC37J84EVM ( Texas Instruments)
ADS42JB49EVM ( Texas Instruments)
Besides, 10 additional signals have been added “F2_HB(0 to 9)”. Refer to the NG-LARGE dev Kit schematic.
The mapping with the NG-LARGE is indicated in the document “MFC_mapping.xlsx”
FMC CONNECTOR N°2 (J2) MAPPING :
NG-large Pins | 14 bits/ 156,25MSPS 2xADC ADS42JBX9 EVM | DAC38J84 EVM | Additional HSSL lanes on FMC signals |
HSSL3_TX4P |
| DAC_lane0_P |
|
HSSL3_TX4N |
| DAC_lane0_N |
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HSSL3_TX3P |
| DAC_lane1_P |
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HSSL3_TX3N |
| DAC_lane1_N |
|
HSSL3_TX1P |
| DAC_lane2_P |
|
HSSL3_TX1N |
| DAC_lane2_N |
|
HSSL3_TX2P |
| DAC_lane3_P |
|
HSSL3_TX2N |
| DAC_lane3_N |
|
HSSL3_RX4P | DA0P (CML) |
|
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HSSL3_RX4N | DA0N (CML) |
|
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HSSL3_RX3P | DA1P (CML) |
|
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HSSL3_RX3N | DA1N (CML) |
|
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HSSL3_RX1P |
|
| DP3_M2C_P |
HSSL3_RX1N |
|
| DP3_M2C_N |
HSSL3_RX2P |
|
| DP2_M2C_P |
HSSL3_RX2N |
|
| DP2_M2C_N |
NG-LARGE pins Signal name |
IO_B21D03N_DQS_SWDI F2_HB0 IO_B21D03P_DQS_SWDI F2_HB1 IO_B21D05N_DQ F2_HB2 IO_B21D05P_DQ F2_HB3 IO_B21D06N_CAL F2_HB4 IO_B21D06P_DQ F2_HB5 IO_B21D17N_DQ_SWSI F2_HB6 IO_B21D07P F2_HB7 IO_B21D07N F2_HB8 IO_B21D08N F2_HB9 IO_B22D09N FMC_B6 IO_B22D10N FMC_DIR_CTRL IO_B01D03N FMC_I2C_SCL IO_B01D03P FMC_I2C_SDA IO_B22D08N FMC_SCLK IO_B22D09P FMC_SDIO IO_B22D11P FMC_SDO IO_B22D07N FMC_SEN_B5 IO_B22D08P FMC_SEN_DAC IO_B22D10P FMC_SEN_LMK IO_B01D01N REQ_SYNC IO_B21D02N_DQ_SWSO DAC38_SYNC_N IO_B21D02P_DQ_SWSO DAC38_SYNC_P IO_B22D17P_DQ_SWSI ADS42_SYNC_P IO_B22D17N_DQ_SWSI ADS42_SYNC_N IO_B22D12N_DQ OVRA IO_B21D01N_DQ_SWDO CAR_SYSREF_N IO_B21D01P_DQ_SWDO CAR_SYSREF_P IO_B21D04N_DQ_SWSI GTX_CLK_N IO_B21D04P_DQ_SWSI GTX_CLK_P HSSL3_CLKREFN Dev_CLKREF_N HSSL3_CLKREFP Dev_CLKREF_P |
Some GPIOs are also available through the FMC connectors N°1 (signals F1_IO (0 to 15) and N°2 (signals F2_HB0 to 9)) in addition to the minimum of signals to drive the FMC boards. .
I2C functions
I/V monitoring
I/V monitoring is possible via the I2C interface (ADG728 multiplexer and an ADS1115 ADC) and the ANGIE module.
For each acquisition 2 phases must be done: 1) select the multiplexer port 2) sample the ADC (ADS1115).
I2C address | Multiplexer port | Value measured | |
0x4D (ADG728 mux) | S1 | 2V5 current | |
S2 | 3V3 current | ||
S3 | 1V2 Core current | ||
S4 | 12V current | ||
S5 | V_DDR current | ||
S6 | HSSL 2V5A current | ||
S7 | HSSL TxVddA current | ||
S8 | HSSL Vcore current | ||
Ox4C (ADG728 mux) | S1 | 2V5D voltage | |
S2 | 3V3D voltage | ||
S3 | VddCore voltage | ||
S4 | - | ||
S5 | V_DDR voltage | ||
S6 | HSSL 2V5A voltage | ||
S7 | HSSL TxVddA voltage | ||
S8 | HSSL_Core voltage |
I2C address | ADC port | Measured mux output | |
0x48 (ADS1115) | AIN0 | MUX1 (0x4D) | |
AIN1 | MUX2 (0x4C) | ||
AIN2 | Direct Vdd_Sense sampling |
Temperature sensor
The on board temperature sensor can be read via I2C bus with the ANGIE module at the address 0x49. (LM73CIMK-0 circuit).
Identification eeprom
The on board 16Kbytes eeprom (24LC128) can be read via I2C bus with the ANGIE module at the address 0x51.