NG-LARGE NX1H140ATSP is the second generation of Radiation Hardened By Design (RHBD) SRAM-based FPGA developped by NanoXplore, manufactured on the rad-hard 65nm CMOS technology platform for space applications from ST Microelectronics. The programmable matrix designed architecture, larger than the one built for the NG-MEDIUM NX1H35AS on the same technology, is based on a similar interconnect architecture made of 4-input Look-up tables with LUT extender to support wider operations, configurable DFF, Coarse Grain Blocks with user configurable memories and Digital Signal Processing units, etc… offering a high logic density.
In addition, the NG-LARGE NX1H140ATSP offers the following additional features:
24 High-Speed Serial Links from 0.70 to 6.25Gbps compliant to most serial I/O protocols, ie Space-Fibre, Serial Rapid I/O, ESIstream and JESD204B
an Embedded Hard IP Processor core which is a RHBD single-core ARM Cortex-R5
This page provides a list of all available documentations related to use efficiently the NG-LARGE NX1H140ATSP.
Documentation
As a radiation hardened FPGA, the NG-LARGE NX1H140ATSP is currently going through a qualification process for flight applications. The datasheet of the NG-LARGE follow the following rules:
SPACE datasheet applies for RHBD qualified component : SPACE NX1H140ATSP Datasheet V1.0.13
The NG-LARGE NX1H140ATSP is configured by loading the bitstream into internal configuration memory using one of these following programming modes:
JTAG,
Slave Parallel 8 bits,
Slave Parallel 16 bits,
Slave SpaceWire, compliant ECSS-E-ST-50-12C link,
Master SPI, compliant with SPI JESD68.01
The configuration guide documentation described every programming mode with associated features and usages:
The NG-LARGE NX1H140ATSP is assembled in either Ceramic/Hermetic packages for Traditional Space projects as well as Organic package for New Space missions. The packaging & pinout page provides detailed description of the Plastic/Ceramic packaging solutions used to assemble the NG-LARGE NX1H140ATSP and the associated pinout:
The complete NG-LARGE NX1H140ATSP ballout is available in the following page:
The NG-LARGE NX1H140ATSP includes an ARM Cortex R5 Processor as hard macro, the usage of the Cortex R5 is described in the following page:
Given specific configuration and context used to program resources of the FPGA matrix, the size of the bitstream generated may vary based on what is used for the application. The Bitstream Size Estimator gives an estimation on which resources will have an impact on the size of the bitstream:
NanoXplore provides characterized data through IBIS models for temperature and corner case conditions aimed for simulation works. Power consumption estimation can be computed using NXPowerEstimator for any project application given which kind and how many resources will be used to map the design:
NG-LARGE IBIS model for I/O : ng_io_pad_complex.ibis.tar.gz
NX Power estimator for NG-LARGE : NXPowerEstimator_NGLARGE_v1c.xlsm
IPs compatible with NG-LARGE
NanoXplore is willing to develop internal IPs for NG-LARGE use and already work with third-partner providers for some IPs currently available within the NXcore tool, part of the NXmap software chain.