Features
Preplace IP : new feature that allows to call an IP already preplaced, then place it in another project. All TILE and CGB instances are supported. An example is available in the Nxmap User Manual.
Constraint
[Constraint] setSite() command: compliance with LUT DFF and CY / Constraint can be set at any moment before Placing 1/5 (included)
[Constraint] constrainPath: DSP, RF, RAM and CY recognized. Distinction between Hard constrainPath (only instances in path are constrained) and Soft constrainpath (registers connected to all instances in path are constrained too).
[Constraint] reportRegisters: report the list of all registers at any step of progress
[Constraint]NxRegExp: Check Appendix “NxRegExp”
[Constraint]: addBlackbox (IP): Preplacing IP and implement the routed project in the top project. All TILE and CGB instances are supported.
Primitive
[Primitive] NX_GCK: ‘MUX’ mode with input generated into the fabric
[Primitive] NX_RAM: Support of Multi-Register Memory Read Port (case when no pipe at the output)
Logging
[Logging] Options table for bitstreaming in logs
[Logging] Added GCK to reportInstances table
Tool
[Tool] DSP_U : Inferred large multiplications allowed
[Tool] addVlogDefine command: command to override ‘Define’ in verilog file
Bug fix
Constraint
[Constraint] IO: Wrong IO name mustn’t reserve a pad
Logging
[Logging] Termination: TerminationReference only allowed for pads with termination
[Logging] Multiple Emitter: Name of the signal concerned by error is reported to user
[Logging] Termination: No termination for 3.3V for MEDIUM + LARGE / User IO name is reported in case of wrong termination value
Netlist
[Netlist] NX_IOB: generics set by addPad are now passed through the macro cell
[Netlist] NX_PLL_U: ‘use_cal’ set as integer instead of std_logic
Known issues
Changed behavior in Regioning due to new algorithms. It might have an impact on performance.
Appendix
NxRegExp
Impacted methods:
The following methods allow regular expressions / wildcard formats in order to match with multiple instances:
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