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All parameters are user’s defined. Among available parameters :
Global parameters :
Word_clock_freqfreq: Frequency of the word clock (integer value in MHz)Data_sizesize: serialization/deserialization factorNUMBER_OF_DESDES: number of DES in the considered groupNUMBER_OF_SERSER: number of SER in the same groupBANK_NUMBER: the number of the complex bank where the group of SER/DES must be located
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Apply to all DES in the considered group. Those parameters are the same that apply to NX_IOB_I
Des_pad_type: electrical standard of all DES in the considered groupDes_differentialDes_terminationDes_termination_referenceDes_weakTerminationDes_turboDes_inputSignalSlopeDes_location: number of the I/O in the considered bank (array of strings like (“01P”, “05N”, “12P”"01P", "05N", "12P")Des_delay_on: must be removed from parameters listDes_dpath_dynamic: when ‘1’'1', allows automatic calibrationDes_inputDelayLine: default delay value for each DES (array of strings). Note that the input delay value is overridden by the optimal value during the calibration process.Des_trainingValue: word value to be recognized during the data/clock alignment sequence
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Apply to all SER in the considered group. They are the same that apply to NX_IOB_O
Ser_pad_typeSer_differentialSer_slewRateSer_outputCapacitySer_location: number of the I/O in the considered bank (array of strings like “02P”, “06N”, “15P”"02P", "06N", "15P")Ser_delay_on: should be removed from parameters listSer_spath_dynamic: ????Ser_outputDelayLine: one static value for each SER (array of strings).Ser_outputDelayLinevalue is not affected by the calibration process.ser_trainingValue: word value to be sent during the data/clock alignment sequence on the receiver side
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Other parameters are automatically deduced from the user’s defined ones |
Basic recommendations for correct implementation:
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Clocks related inputs and outputs
CLKIN_SERDES- input : word clock input
SCK_OUT- output : internally generated word clock image distributed on the low skew network (clock tree) for optional usage in other portions of the design. Of course this clock is also used in the IP Core.
DCK_OUT– output : the data/clock alignment requires an independent clock for reading and writing delay registers. This clock is generated in the same CKG block, and its frequency the word clock frequency divided by 4. It’s distributed by a clock tree. Optionally, this clock can be used in other portions of the design.
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Control related inputs and outputs
RST_OUT– output : This signal remains high while the PLL is not locked (the internally generated clocks are not working properly).RST_OUTcan be used to reset external IP Core logic or to prevent activity until it comes low.
LAUNCH_CALIB- input : AfterRST_OUThas been de-asserted, a high pulse of 2 to 16 word clock periods must be applied to this input in order to start the data/clock and word alignment process (this process is also called CALIBRATION).
TRAINING_REQUEST_OUT- output : Active high. The IP Core informs that it requires an external transmitter device to send continuously a specific value – called “DES_TrainingValue” to the deserializers (receivers) being part of the IP Core.TRAINING_REQUEST_OUTgoes back low after the calibration (bit & word alignment) process is complete (seeCALIB_DONEoutput).
TRAINING_ACK_IN- input : When high, the transmitter informs that it received the request for receiver calibration, and it’s currently sending the required training value.
TRAINING_REQUEST_IN- input : Active high. If the IP Core is used as transmitter, it must send the expected “SER_TrainingValue” to the receiver. This is the training request signal coming from the external receiver device.
TRAINING_ACK_OUT- output : When high, the IP Core transmitter informs that it received the calibration request from the receiver, and it’s currently sending the required “SER_trainingValue”.TRAINING_ACK_OUTmust go back low ifTRAINING_REQUEST_INgoes low.
CALIB_DONE- output : Goes high when the calibration (DESerializers data/clock and word alignment) process is complete.
CALIB_ERROR- output : Goes high if the calibration could not complete successfully.
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Data related inputs and outputs
RX(MD-1 downto 0)- input : DESerializer(s) input pad name. “MD” is the number of deserializers used in the current SER/DES group.
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The SERDES IP Core is able to implement multi-channel deserialization. Tacking as reference the word clock (CLKIN_SERDES) it generates automatically the required clocks
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The SERDES IP Core ensures data/fast clock alignment on each RX input. It also provides word alignment.
DOUT(MD-1:0)(N-1:0)(array of outputs) : Deserialized and word aligned output to the fabric.“MD” is the number of deserializers, “N” is the deserialization factor – common to all deserializers and serializers of a same group.
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Each deserializer deserializes its own stream and provides a parallel DOUT word after the calibration process (bit alignment and word alignment) properly completes.
TX(MS-1 downto 0)- output : Serializer(s) output pad name. “MS” is the number of serializers used in the current SER/DES group.
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The SERDES IP Core is able to implement multi-channel serialization and deserialization. Tacking as reference the word clock (CLKIN_SERDES) it generates automatically the required clocks.
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Each SERializer can use the output delay line to delay the output data relatively to the the bit clocks. The delay is fixed for a given bitstream. It can be adjusted via the GRPX_ser_outputDelayLine parameter.
DIN(MS-1:0)(N-1:0)- array of inputs : Inputs for the words to be serialized (coming from fabric). “MS” is the number of serializers, “N” is the serialialization factor – common to all serializers and deserializers of a same group.
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