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The same reasoning applies for the CK / CK# pins and the dfi_dram_clk_disable signal.
Users should configure properly the DFI IP using this package, and take care that all arrays (DQ, AD, BA, …) declared in this VHDL package are complete and coherent.
Bank and pad indexes during pad declaration are using logical locations.
E.G:
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|---|---|---|
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constant DQ2 : pad_t := (1, 9); |
This line means pad DQ2 is on Bank1 (logical index), and occupies pad #9 (physical) (corresponding to pad D05N).
| Code Block | ||
|---|---|---|
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type array_iob is array (0 to NB_IOB-1) of string; -- IOB |
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constant IDX_IOB : array_iob := ("IOB10", "IOB11"); |
The above line makes a correspondence between physical and logical bank indexes.
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These signal widths shall be reflected at the DFI Interface.
I.E. Using NB_RAS = 2 means all 4 phase-replicated dfi_ras_pN shall have a width of 2.
If the user wishes to duplicate a pin, this duplication shall be reflected at the DFI Interface.
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pad_t is a custom VHDL type declared inside the package;
| Code Block | ||
|---|---|---|
| ||
type pad_t is record |
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bank : natural; -- Index of bank |
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pad : natural; -- Index of pad |
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end record pad_t; |
Configuration package file of Evaluation Kit DK625v* shall be included as an example.
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The Update interface in only used when the DFI IP needs to re-calibrate its internal delay lines. It does so by asserting its dfi_phyupd_req_o output signal, then waits on its dfi_phyupd_ack_i input signal.
Once asserted, it shall internally go through re-calibration. It shall de-assert its dfi_phy_req_o output signal once re-calibration is complete.
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Name | Direction | Width | Description |
ser_ck_o | Out | NB_CK |
|
ser_ad_o | Out | NB_AD |
|
ser_ba_o | Out | NB_BA |
|
ser_cke_o | Out | NB_CKE |
|
ser_odt_o | Out | NB_ODT |
|
ser_cs_o | Out | NB_CS |
|
ser_dqs_io | InOut | NB_DQS |
|
ser_dq_io | InOut | NB_DQ |
|
ser_msk_o | Out | NB_DM |
|
ser_cas_o | Out | NB_CAS |
|
ser_ras_o | Out | NB_RAS |
|
ser_wen_o | Out | NB_WEN |
|
ser_rst_o | Out | NB_RST | Unused in DDR2. |
Command pads use the CmdPadType generic electrical standard, while data (DQS / DQ and DM) pads use the DqsDqDmPadType generic electrical interface.
DQ pads use the fpgaDqTerm termination value, while DQS pads use the fpgaDqsTerm termination value, both of which need to be filled in as strings.
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These configurations were tested on NanoXmap 2.9.4, using useCDCForMC = false and bypassInit = false. Different results may be expected if using different parameters.
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When setting the generic bypassInit to true, extra care should be taken after realizing DDR initialization.
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