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Figure 1: High level view of the DDR subsystem
List of changes
Introduction
High-level block diagram
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Figure 1 The previous figure shows a high-level view of the DDR memory subsystem. The system may be seen as 4 different entities. A Memory Controller (MC), a DFI IP, N PHY (I/O Banks), and M DDR memory.
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Refer to the additional documentation for more information on the DFI / DDR2 Specifications
Document | Description |
DDR PHY Interface, Version 4.0 | Description of signals and their relationships that make up the DFI Interface |
DDR2 SDRAM Specification JESD79-2E | JEDEC Standard defining the SDRAM DDR2 protocol and functionality. |
NanoXplore Library Guide |
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NanoXplore FPGA NG-Medium User Guide |
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The pinout_pack configuration VHDL package file must contain the following constants:
Name | Type | Description | Affects width of |
NB_IO | Natural | Number of I/Os per Bank, 30 for ng-medium |
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NB_IOB | Natural | Number of I/O banks the DDR Interface spans over. |
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NB_DQ | Natural | Number of DQ pins | dfi_wrdata_i (twice) dfi_rddata_o (twice) ddr_dq_io |
NB_DQS | Natural | Number of DQSP pins | dfi_wrdata_en_i dfi_rddata_en_i dfi_rddata_valid_o dfi_data_byte_disable_i ddr_dqs_io |
NB_DM | Natural | Number of Data Mask pins | dfi_wrdata_mask_i ddr_dm_o |
NB_AD | Natural | Number of address pins
| dfi_address_i ddr_ad_o |
NB_BA | Natural | Number of Bank Address pins | dfi_bank_i ddr_ba_o |
NB_CKE | Natural | Number of CKE pins | dfi_cke_i ddr_cke_o |
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NB_ODT | Natural | Number of ODT pins | dfi_odt_i ddr_odt_o |
NB_CS | Natural | Number of CS pins | dfi_cs_n_i ddr_cs_o |
NB_CK | Natural | Number of CKP pins | dfi_dram_clk_disable_i ddr_ck_o |
NB_CAS | Natural | Number of CAS pins | dfi_cas_n_i ddr_cas_o |
NB_RAS | Natural | Number of RAS pins | dfi_ras_n_i ddr_ras_o |
NB_WEN | Natural | Number of WEN pins | dfi_wen_n_i ddr_wen_o |
NB_RST | Natural | Number of Reset pins (DDR3 only) | dfi_reset_n_i ddr_rst_o |
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The user should then fill the following arrays with the corresponding pads:
Name | Number of elements | Type of elements | Description |
IDX_IOB | NB_IOB | string | Correspondence between logical indexing and actual banks used in the FPGA |
DQ | NB_DQ | pad_t |
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DQSP | NB_DQS | pad_t |
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DQSN | NB_DQS | pad_t |
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DM | NB_DM | pad_t |
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AD | NB_AD | pad_t |
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BA | NB_BA | pad_t |
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CKP | NB_CK | pad_t |
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CS | NB_CS | pad_t |
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ODT | NB_ODT | pad_t |
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CKE | NB_CKE | pad_t |
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CAS | NB_CAS | pad_t |
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RAS | NB_RAS | pad_t |
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WEN | NB_WEN | pad_t |
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The following table makes a correspondence between Logical Indexes and their physical locations:
Generics
Name | Type | Default Value | Description |
calClockDivPowerOf2 | Integer | 0 | By which power of 2 to divide ck_ddr for it to fall within 100-200 MHz |
invertOutputCK | boolean | false | Inverts Clock output. Set to true on DK625V*. |
bypassInit | boolean | false | Set to true if using a clock ratio other than 4, or if you wish to let the memory controller realize DDR initialization Refer to section « 4 Limitations and compatibility with DFI 4.0 » if using true |
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tCK | Integer | 8000 | DDR tCK in picoseconds |
tRPA | Integer | 25000 | DDR tRPA in picoseconds |
tRFC | Integer | 327000 | DDR tRFC in picoseconds |
tRCD | Integer | 20000 | DDR tRCD in picoseconds |
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casLatency | Integer | 5 | DDR Cas Latency to be set during initialization |
writeRecovery | Integer | 2 | DDR Write Recovery (in cycles) |
sequentialBurst | Boolean | True | Used during mode register initialization |
rttNomnial | Integer | 75 | Shall be 50, 75 or 150. Used during mode register initialization |
differentialDQS | Boolean | True | True to configure and use differential DQS |
outputDriveImpendanceCtrl | Boolean | True | True for full strength False for reduced strength |
additiveLatency | Integer | 0 | Additive Latency |
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simu | Boolean | false | Cuts down wait times during initialization. |
fpgaDqTerm | String | “75” | Termination value to be used for FPGA DQ pads |
fpgaDqsTerm | String | “75” | Termination value to be used for FPGA DQS pads |
DqsDqDmPadType | String | “SSTL_1.8V_I” | Shall be set to “SSTL_1.8V_I” or “SSTL_1.8V_II” |
CmdPadType | String | “SSTL_1.8V_I” | Shall be set to “SSTL_1.8V_I” or “SSTL_1.8V_II” |
DqsDqDmSlewRate | String | “Fast” | SlewRate on Data pads. Fast is recommended. |
CmdSlewRate | String | “Fast” | SlewRate on Command pads. Fast is recommended. |
DataTurbo | String | “True” | DQ/DQS Input pad config. True is recommended. |
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Refer to DFI Specification 4.0 for more information on these signals.
Control Interface
Name | Direction | Width | Description |
dfi_address_pN_i | in | DFI_ADDRESS_WIDTH |
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dfi_bank_pN_i | in | DFI_BANK_WIDTH |
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dfi_cas_n_pN_i | in | NB_CAS |
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dfi_cke_pN_i | in | NB_CKE |
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dfi_cs_n_pN_i | in | NB_CS |
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dfi_odt_pN_i | in | NB_ODT |
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dfi_ras_pN_i | in | NB_RAS |
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dfi_we_n_pN_i | in | NB_WEN |
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dfi_reset_n_pN_i | in | NB_RST-1 | DDR3 Only. |
Write Data Interface
Name | Direction | Width | Description |
dfi_wrdata_pN_i | in | DFI_DATA_WIDTH |
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dfi_wrdata_en_pN_i | in | DFI_DATA_ENABLE_WIDTH |
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dfi_wrdata_mask_pN_i | in | DFI_DM_WIDTH | One bit per bytelane |
Read Data Interface
Name | Direction | Width | Description |
dfi_rddata_en_pN_i | in | DFI_DATA_ENABLE_WIDTH |
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dfi_rddata_wN_o | out | DFI_DATA_WIDTH |
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dfi_rddata_valid_wN_o | out | DFI_READ_DATA_VALID_WIDTH |
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Update Interface
Name | Direction | Width | Description |
dfi_ctrlupd_req_i | in | 1 | NC |
dfi_ctrlupd_ack_o | out | 1 | Always ‘0’ |
dfi_phyupd_req_o | out | 1 |
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dfi_phyupd_type_o | out | 2 | NC – Always “00” |
dfi_phyupd_ack_i | in | 1 |
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Once asserted, it shall internally go through re-calibration. It shall de-assert its dfi_phy_req_o output signal once re-calibration is complete.
Status Interface
Name | Direction | Width | Description |
dfi_data_byte_disable_i | in | DFI_DATA_BYTE_DISABLE_WIDTH |
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dfi_dram_clk_disable_i | in | NB_CK |
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dfi_freq_ratio_i | in | 2 | 0b00 = 1:1 0b01 = 1:2 0b10 = 1:4 Only 1:4 frequency ratio is supported |
dfi_init_complete_o | out | 1 |
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dfi_init_start_i | in | 1 | DFI won’t start unless this signal is asserted. Necessary to specify starting freq. Ratio, and byte lanes disabled |
Additional Inputs
Name | Direction | Width | Description |
ck_sdr_i | in | 1 | SDR clock (F = 2xFDDR) |
ck_dfi_i | in | 1 | DFI Memory Controller clock (F = ¼ of FDDR) |
ck_ddr_i | in | 1 | DDR clock (F = FDDR, or divided by a power of 2 to fall within 100-200 MHz). This clock is only used for delay line calibration. |
ck_work_i | in | 1 | Work clock (F = ½ of FDDR) |
err_o | out | 1 | Error out signal, asserted while re-calibrating, during a DFI |
rst_n_work_i | in | 1 | Reset signal in ck_work clock domain |
rst_n_dfi_i | in | 1 | Reset signal in memory controller clock domain |
Memory Interface
Name | Direction | Width | Description |
ser_ck_o | Out | NB_CK |
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ser_ad_o | Out | NB_AD |
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ser_ba_o | Out | NB_BA |
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ser_cke_o | Out | NB_CKE |
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ser_odt_o | Out | NB_ODT |
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ser_cs_o | Out | NB_CS |
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ser_dqs_io | InOut | NB_DQS |
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ser_dq_io | InOut | NB_DQ |
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ser_msk_o | Out | NB_DM |
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ser_cas_o | Out | NB_CAS |
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ser_ras_o | Out | NB_RAS |
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ser_wen_o | Out | NB_WEN |
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ser_rst_o | Out | NB_RST | Unused in DDR2. |
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Timing parameters
Control Interface
Parameter | Value | Unit | Description |
tctrl_delay | 10 | DFI clock cycles | Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. |
Write Data Interface
Parameter | Value | Unit | Description |
tphy_wrdata | 3 | DFI PHY clock cycles | Specifies the number of DFI PHY clock cycles between when the dfi_wrdata_en signal is asserted to when the associated write data is driven on the dfi_wrdata signal |
tphy_wrdelay | 0 | DFI PHY clock cycles | Specifies the number of DFI PHY clock cycles of additional delay that the PHY must insert between the write data enable and write data once data has been captured from the DFI bus. |
tphy_wrlat | AL+CL-4 = WL-3 | DFI PHY clock cycles | Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the dfi_wrdata_en signal is asserted. |
Read Data Interface
Parameter | Value | Unit | Description |
tphy_rdlat | 35 | DFI PHY clock cycles | Specifies the maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of the dfi_rddata_valid signal |
trddata_en | AL+CL-2 = RL-2 | DFI PHY clock cycles | Specifies the number of DFI PHY clock cycles from the assertion of a read command on the DFI to the assertion of the dfi_rddata_en signal. |
Status Interface
Parameter | Value – max | Unit | Description |
tdram_clk_disable | 10 | DFI clock cycles | Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. |
tdram_clk_enable | 10 | DFI clock cycles | Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value |
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DFI Frequency ratio change protocol is not supported.
Only a DFI Frequency Ratio of 4 is supported
Read commands shall only be sent on phase p0.
The user should take care of using NanoXmap’s PrePlace feature on the following registers:
◦ <your_hierarchy>|<dfi_instance_name>|inst_top_dfi|ins_dfi|ins_dfi_core|dfi_rddata_w0_o_reg[*]
◦ <your_hierarchy>|<dfi_instance_name>|inst_top_dfi|ins_dfi|ins_dfi_core|dfi_rddata_w1_o_reg[*]
◦ <your_hierarchy>|<dfi_instance_name>|inst_top_dfi|ins_dfi|ins_dfi_core|dqs_r_reg[0-3]
These registers should be placed as closely as possible to the corresponding IO Banks.
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When setting the generic bypassInit to true, extra care should be taken after realizing DDR initialization.
Once the initialization phase is over; the user should realize 3 BL8 Read accesses.
The first two shall be ‘back-to-back’. The last one should be on the same phase (p0, ..., p3) on the first ones.
All following read commands shall be sent on the same phase (p0, ..., p3) as the first ones.
There is no guarantee that these read accesses will return the expected data, and they won’t generate any rddata_valid signals.
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