Revision | Date | Originator | Comments |
1.0 | 04/02/2019 | D. CHAMEREAU | |
1.1 | 01/16/2020 | D. CHAMEREAU | Correcting the configuration setup table. Adding pin 1 on jumpers on Top assembly Drawing + level for switches. |
1.2 | 01/30/2020 | D. CHAMEREAU | Converting the pin mapping between NG-LARGE pin names and connectors/Signal Name for Nxmap. |
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Config. mode | J41 = MOD2 | J43 = MOD1 | J42 = MOD0 | Comments |
Mode 0: Master SPI | Pos. 2-3 | Pos. 2-3 | Pos. 2-3 | The SPI flash board must be plugged on J29 connector |
Mode 1: Master SPI +SPI Power Supply | Pos. 2-3 | Pos. 2-3 | Pos. 1-2 | The SPI flash board must be plugged on J29 connector |
Mode 2: Slave Space Wire | Pos. 2-3 | Pos. 1-2 | Pos. 2-3 | J17 is the configuration mode connector by the spacewire interface. |
Mode 3: Reserved (Jtag only) | Pos. 2-3 | Pos. 1-2 | Pos. 1-2 | |
Mode 4 : Slave 8 bits parallel | Pos. 1-2 | Pos. 2-3 | Pos. 2-3 | |
Mode 5 : Slave 16 bits parallel | Pos. 1-2 | Pos. 2-3 | Pos. 1-2 | |
Mode 6 : Reserved | Pos. 1-2 | Pos. 1-2 | Pos. 2-3 | |
Mode 7: Test Mode | Pos. 1-2 | Pos. 1-2 | Pos. 1-2 |
An optional slave 8 bits parallel mode is possible via an other Dev Kit and via the connector J40, configuring the jumpers J25 and J28. Please to join the support for more informations.
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Green Leds (Active to 0) | NG-Large Pins | Bank | Switches Right Position : 0V Left Position : 3.3V | NG-Large Pins | Bank |
D1 D2 D3 D4 D5 D6 D7 D8 | IO_B11D05N IO_B11D05P IO_B11D06N IO_B11D06P IO_B11D07N IO_B11D07P IO_B11D08N IO_B11D08P | 11 | SW1 SW2SW3SW3 SW5 SW4SW7 SW5SW9 SW6SW11 SW7SW13 SW8SW15 | IO_B12D12P IO_B12D12N IO_B12D11P IO_B12D11N IO_B12D10P IO_B12D10N IO_B12D09P IO_B12D09N | 12 |
Push buttons (pressed = 0V) | NG-Large Pins | Bank | |||
PB1SW2 PB2SW4 PB3SW6 PB4SW8 PB5SW10 PB6SW12 PB7SW14 PB8SW16 | IO_B11D01N IO_B11D01P IO_B11D02N IO_B11D02P IO_B11D03N IO_B11D03P IO_B11D04N IO_B11D04P | 11 |
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NG-LARGE Carrier Dev Kit Signals | Dir. | FMC Std signals | EV12AD500A pins | |
Gbits transceivers | DP0_M2C_P/_N | ASL1p/n ( CML logic) | ||
Gbits transceivers | DP1_M2C_P/_N | ASL3p/n ( CML logic) | ||
Gbits transceivers | DP2_M2C_P/_N | ASL2p/n ( CML logic) | ||
Gbits transceivers | DP3_M2C_P/_N | ASL0p/n ( CML logic) | ||
SYNC_P /n (LVDS) | HB17_p /n | SYNCTRIG_P /N (LVDS) | ||
SYNCO (LVDS) | CLK1_M2C_P /N | SYNCOP/N (LVDS) | ||
SSO (LVDS) | GBTCLK0_M2C_P | SSOp/n (LVDS) | ||
SPI_mode | HA18_N | SPI bus shared control | ||
Reset DUT | HA19_P | reset | ||
SCLK (2.5V) | HA19_N | SCLK | ||
Cs (2.5V) | HA20_P | csn | ||
Mosi (2.5V) | HA20_N | mosi | ||
Miso (2.5V) | HB03_P | miso | ||
Channel A data ready | HB06_P/N | P/N_ADR | ||
Channel A control Bits 2 | HB04_P/N | P/N_AFU2 | ||
Channel A control Bits 1 | HA12_P/N | P/N_AFU1 |
Board requirements:
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Setup ( Ref. EV12AD5x0‐EK VITA 57 FMC DUAL 12b ADC Evaluation kit)
FMC CONNECTOR N°1 (J1) MAPPING
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