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Attribute:
NxInit
NxPort
NxUse
SynKeep
SynPreserve
Board:
Scope
SwichBlink
ThermalSensor
Component
ClockSwitch
DspConfig
IoConfig
PllConfig
RamConfig
RfbConfig
Service
Soc
WfgConfig
Design
DelayIo
DspCascaded
DspMultAcc
DspTranspose
LowskewManagement
MemInfer
Init
Ram
Ip
CrossDomain
Ddr2Dfi
HsslEsistream
R5AxiMaster
R5AxiSlave
R5Jtag
Serdes
SpacewireLoopback
SpacewireRoadmap
MappingDirective
Adder
BlackBox
Memory
Pad
Parameter
Registered
PlacingConstraint
Aperture
ConstrainPath
DspLocation
ExportSites
Focus
Obstruction
PreplaceIp
RamLocation
Region
RingLocation
Site
StaConstraint
ClockGroup
DelayPath
FalsePath
GeneratedClock
InputOutputDelay
ReportPath
Testcase content
Each testcase of this application note contains the following fields:
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The user can apply a minimum and a maximum data arrival time on inputs and outputs using respectively setInputDelay and setOutputDelay NXpython methodmethods.
These methods need a created clock to be set.
...
| Code Block |
|---|
| +--------+-----------+----------------------------------+---------------------------------+------------+------------+----------------+--------+--------------------------------+
| | No. | Slack | Source | Target | Data Delay | Clock Skew | Setup/Recovery | Depth | Note |
| +--------+-----------+----------------------------------+---------------------------------+------------+------------+----------------+--------+--------------------------------+
| | 1 | -17.951ns | Pin: i_cpt_2|s_cpt_out_reg[0].CK | Pin: cpt_out[0].I | 20.240ns | -7.711ns | - | 1 | setOutputDelay: 10.000ns (RR) |
| | 2 | -14.913ns | Pin: i_cpt_2|s_cpt_out_reg[2].CK | Pin: cpt_out[2].I | 17.202ns | -7.711ns | - | 1 | setOutputDelay: 10.000ns (RR) |
| | 3 | -13.769ns | Pin: i_cpt_2|s_cpt_out_reg[1].CK | Pin: cpt_out[1].I | 16.058ns | -7.711ns | - | 1 | setOutputDelay: 10.000ns (RR) |
| | 4 | -13.678ns | Pin: i_cpt_2|s_cpt_out_reg[3].CK | Pin: cpt_out[3].I | 15.967ns | -7.711ns | - | 1 | setOutputDelay: 10.000ns (RR) |
| | 5 | -5.233ns | Pin: cpt_in[1].O | Pin: i_cpt_0|s_cpt_out_reg[3].L | 21.756ns | 7.614ns | 1.091ns | 2 | setInputDelay: 10.000ns (RR) |
| | 6 | -5.233ns | Pin: cpt_in[1].O | Pin: i_cpt_0|s_cpt_out_reg[2].L | 21.756ns | 7.614ns | 1.091ns | 2 | setInputDelay: 10.000ns (RR) |
| | 7 | -5.233ns | Pin: cpt_in[1].O | Pin: i_cpt_0|s_cpt_out_reg[1].L | 21.756ns | 7.614ns | 1.091ns | 2 | setInputDelay: 10.000ns (RR) |
| | 8 | -5.233ns | Pin: cpt_in[1].O | Pin: i_cpt_0|s_cpt_out_reg[0].L | 21.756ns | 7.614ns | 1.091ns | 2 | setInputDelay: 10.000ns (RR) |
| | 9 | -963ps | Pin: cpt_in[3].O | Pin: i_cpt_0|s_cpt_out_reg[3].L | 17.486ns | 7.614ns | 1.091ns | 2 | setInputDelay: 10.000ns (RR) |
| | 10 | -963ps | Pin: cpt_in[3].O | Pin: i_cpt_0|s_cpt_out_reg[2].L | 17.486ns | 7.614ns | 1.091ns | 2 | setInputDelay: 10.000ns (RR) |
|
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
ReportPath
Description:
The user can generate timing reports between two pins or two registers with respectively reportPath or addReportPath and reportTiming or addReportTimingPath NXpython methods.
The aim of reportPath or addReportPath is to indicate the detailed path between 2 pins of 2 instances and all the instances within the path with associated delay for each step.
reportPath or addReportPath expect a Port or a Pin as an argument
Hereafter an example for both methods:
| Code Block | ||
|---|---|---|
| ||
Timing_analysis = p.createAnalyzer()
Timing_analysis.reportPath(maximumSlack = 500, searchPathsLimit = 10, source = getPort('in_1'), target = getPin('i_clock_0|out_1_reg.I'))
Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportPath(source = getPin('i_clock_0|counter_1_reg[1].CK'), target = getPin('i_clock_0|counter_1_reg[1].I'))
Timing_analysis.launch({'maximumSlack': 500, 'searchPathsLimit': 10, 'conditions': sta_condition}) |
The aim of reportTiming or addReportTimingPath is to check the required frequency is reached between 2 registers.
reportTiming or addReportTimingPath expect a Port or a Register as an argument
Hereafter an example for both methods:
| Code Block | ||
|---|---|---|
| ||
Timing_analysis = p.createAnalyzer()
Timing_analysis.reportTiming(maximumSlack = 500, searchPathsLimit = 10, source = getRegister('i_clock_0|clk_fabric_reg'), target = getRegister('i_clock_0|counter_reg[0]'))
Timing_analysis = p.createAnalyzer()
Timing_analysis.addReporTimingPath(source = getRegister('i_clock_0|clk_fabric_reg'), target = getRegister('i_clock_0|clk_fabric_reg'))
Timing_analysis.launch({'maximumSlack': 500, 'searchPathsLimit': 10, 'conditions': sta_condition}) |
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock reportPath addReportPath reportTiming addReportTimingPath removeReportPath removeReportTimingPath removeTimingConstraint resetTimingConstraints getRegister getPin getPort |
Table: StaConstraint ReportPath environment
Option: There are two options to check the impact of these constraints:
No option: No created clock and no report.
ReportPath: Clock are created and path reports generated
ReportTiming: Clock are created and timing reports generated
NanoXmap check: After project launching, the user can check there is a report generated for the required paths.
ReportPath option:
REPORTER_path_0_worstcase_routed.timing and REPORT_path_1_worstcase_routed.timing are generated with respective required path:
| Code Block |
|---|
| Reporting longest paths for REPORTER_path_0
| +--------+--------+-------------+----------------------------+------------+------------+----------------+--------+--------+
| | No. | Slack | Source | Target | Data Delay | Clock Skew | Setup/Recovery | Depth | Note |
| +--------+--------+-------------+----------------------------+------------+------------+----------------+--------+--------+
| | 1 | - | Pin: in_1.O | Pin: i_clock_0|out_1_reg.I | 10.145ns | - | - | 0 | |
| +--------+--------+-------------+----------------------------+------------+------------+----------------+--------+--------+
| | Total | 1 | |
| +-------------------------------+--------------------------------------------------------------------------------+--------+ |
| Code Block |
|---|
| Reporting longest paths for REPORTER_path_1
| +--------+--------+------------------------------------+-----------------------------------+------------+------------+----------------+--------+--------+
| | No. | Slack | Source | Target | Data Delay | Clock Skew | Setup/Recovery | Depth | Note |
| +--------+--------+------------------------------------+-----------------------------------+------------+------------+----------------+--------+--------+
| | 1 | - | Pin: i_clock_0|counter_1_reg[1].CK | Pin: i_clock_0|counter_1_reg[1].I | 1.961ns | - | - | 2 | |
| +--------+--------+------------------------------------+-----------------------------------+------------+------------+----------------+--------+--------+
| | Total | 1 | |
| +------------------------------------------------------+---------------------------------------------------------------------------------------+--------+ |
ReportTiming option:
DOMAIN_clk_main_to_clk_main_Routed_worstcase.timing is generated with required timing path:
| Code Block |
|---|
| Summary of DOMAIN_clk_main_to_clk_main
| +---------------------------------------+--------------------------+-------------------------------------------+--------------------------------------------+
| | Domain | Frequency | Hold/Removal Summary | Setup/Recovery Summary |
| +-------------------+-------------------+------------+-------------+---------+--------------+------------------+----------+--------------+------------------+
| | Source | Target | Required | Maximum | Slack | Minimum Data | Minimum Required | Slack | Maximum Data | Maximum Required |
| | | | | | | Arrival Time | Relationship | | Arrival Time | Relationship |
| +-------------------+-------------------+------------+-------------+---------+--------------+------------------+----------+--------------+------------------+
| | clk_main (Rising) | clk_main (Rising) | 25.000 MHz | 368.460 MHz | 1.588ns | 1.588ns | 0ps | 37.286ns | 2.714ns | 40.000ns |
| +-------------------+-------------------+------------+-------------+---------+--------------+------------------+----------+--------------+------------------+
| | Total | 1 |
| +---------------------------------------+-------------------------------------------------------------------------------------------------------------------+
| |
Simulation check: No simulation environment is available for this testcase.
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